Vesa Lehtinen

Discrete-time modeling of polynomial-based interpolation filters in rational sampling rate conversion

If sampling rate conversion (SRC) is performed between arbitrary sampling rates, then the SRC factor can be a ratio of two very large integers or even an irrational number. An efficient way to reduce the implementation complexity of a SRC system in those cases is to use polynomial-based interpolation filters that mimic digitally the hybrid analogue/digital system. In practice, the sampling rate conversion is approximated with a rational factor. In this case, the hybrid analogue/digital model used to represent the SRC process may be represented by an equivalent discrete-time model. The discrete-time modeling of the rational SRC has been used earlier for the zeroth order interpolation. This paper extends this idea to arbitrary polynomial-based interpolation. Furthermore, this paper derives the relation between various polynomial-based interpolation filters (Farrow structure and its modifications) and polyphase FIR model filters. This paper observes possible applications of these relations, such as filter design, implementation complexity reduction, and response distortion analysis.

Digital Mitigation of Transmitter-Induced Receiver Desensitization in Carrier Aggregation FDD Transceivers

Carrier aggregation transmissions in frequency division duplexing devices reduce the duplexing distance between the transmitter (TX) and receiver (RX) bands. As a consequence, the spurious intermodulation distortion products created by the nonlinear RF front-end of the TX may easily extend over to the RX band, potentially causing own RX desensitization. In this paper, we propose an efficient and computationally feasible adaptive digital identification and cancellation technique to mitigate the RX desensitization. We first show that the spurious leakage signal at own RX band depends on an equivalent leakage channel that models the overall signal leakage path including the TX nonlinearities, duplexer filter responses, and RX path. The parameters of the equivalent leakage channel can be efficiently estimated with the least squares or the recursive least squares algorithm, using the actual digital transmit data as a reference, and then used to regenerate and cancel the leakage interference from the received signal. The performance of the proposed technique is evaluated with extensive computer simulations, as well as with practical real-world RF measurements, demonstrating excellent calibration properties with up to 19-dB improvement in singal-to-interference plus noise ratio of the desired received signal.

Gating factor analysis of maximum power reduction in multicluster LTE-A uplink transmission

In radio frequency (RF) power amplifiers (PA), power efficiency, linearity and cost are contradictory requirements. In the Long Term Evolution (LTE) and LTE-Advanced (LTE-A) standards by the Third Generation Partnership Project, maximum power reduction (MPR) is used to relax RF PA requirements in user equipment. In this paper, we analyze the gating factors that determine the MPR in multicluster transmission, a new feature in LTE-A that significantly changes the way unwanted emissions are distributed in the spectrum. The analysis can help in devising more advanced MPR formulas and in development of RF PA linearizers.

On impulse response symmetry of Farrow interpolators in rational sample rate conversion

In this paper, the impulse response symmetry of Farrow interpolation filters and its significance in rational sample rate conversion is addressed. Four methods for ensuring impulse response symmetry are proposed. Comparison of different symmetrization schemes is made, with filters optimized based on the discrete-time impulse response model. The results indicate that optimization based on the discrete-time model often results in better performance than optimization based on the continuous-time model, and that there are significant performance differences between symmetrization schemes.

Implementation of Farrow structure based interpolators with subfilters of odd length

Interpolation filters are used to interpolate new sample values at arbitrary points between existing discrete-time samples. An interesting class of such filters is polynomial-based interpolation filter. These filters can be efficiently implemented using the Farrow structure and its modifications. Traditionally, the polynomial based interpolation filters have been implemented by using Farrow structure with finite impulse response (FIR) subfilters of even length. This paper presents the modification of the Farrow structure, which can have FIR subfilters of odd length. Applying the proposed modification of this paper will result in a natural implementation form for even order Lagrange and spline based interpolators. The obtained results provides more freedom in designing Farrow structure based filters, as structures with odd and even length FIR subfilters may be equally applied. These results are extended to a modified Farrow structure case as well, in which the number of multipliers is nearly halved.

Sampling jitter in charge sampling radio

This article addresses some implementation challenges in the potentially very energy-efficient charge-sampling radios. Alternative ways to implement charge sampler in charge sampling radio are considered, and the impacts and spectral shape characteristics of the sampling jitter induced signal distortion are analytically studied in these cases. The analysis shows that the spectrum of the distortion caused by the sampling jitter in a charge sampling receiver is not necessary flat, which in turn has direct impacts on the receiver design and dimensioning. The validity of the analytical results is verified with computer simulations. In simulations, both white Gaussian noise-type clock jitter and clock jitter generated by a phase-locked-loop oscillator are considered.

On CIC decimator variants - from shifting zeros to the sparse FIR-CIC structure

The cascaded integrator-comb (CIC) filter is an efficient multiplier- free structure for decimation and interpolation. However, due to its narrow stopband notches, it is useful only when the signal of interest has a small bandwidth compared to the input and output sample rates. Consequently, it can only be used in the first (last) few stages of multistage decimators (interpolators). Various modifications have been proposed in order to alleviate this shortcoming. We investigate the modified CIC structure proposed by Saramaki and Ritoniemi and show that its response can be further improved without increasing the implementation complexity. This remodification results in a FIR filter nested inside a CIC decimator, a structure that is already known. We then propose the use of a sparse FIR filter in this nested structure. This results in remarkable attenuation improvements for given complexity, as shown by design examples.

Analysis of rational sample rate conversion using image response combining

Using discrete-time response modelling, we analyse the complicated frequency domain input-output relationship of sample rate conversion with a rational, non-integer factor and address the ambiguity of the concept of frequency response in fractional multirate systems. The dependence of a system response on the phase of a real signal is shown. We develop a method to translate a magnitude response from a higher sample rate to a lower one to allow better comparison between filter properties and system specifications when rational sample rate conversion is used. The method is based on the idea of combining the responses of all (aliased) images of an input frequency into a scalar quantity. The method is hence referred to as image response combining (IRC) and the resulting response function as image-combined magnitude response. Two different IRC schemes are proposed. To overcome the sometimes very high computational complexity of frequency domain IRC, we derive a drastically faster time domain IRC algorithm referred to as sampled autocorrelation of impulse response (SACIR). The paper concentrates on decimation, but the analysis and proposed methods can be easily applied to interpolation, as well.

Linearity Challenges of LTE-Advanced Mobile Transmitters: Requirements and Potential Solutions

In order to provide higher data rates and to improve radio spectrum utilization, 3GPP has introduced the concept of CA in its Release 10 and onward commonly known as LTE-Advanced. The CA technology, particularly when applied in a noncontiguous manner, poses serious design and implementation challenges for radio transceivers, mainly due to the allowed flexibility in the transmitted signal characteristics and the nonlinear RF components in the TX and RX chains. As a consequence, substantial nonlinear distortion may occur that not only degrades the transmitted signal quality but can also affect the concurrent operation of the coexisting receiver when operating in the FDD mode. In this article, the key technical design challenges in terms of linearity requirements for LTE-Advanced mobile terminals are reviewed, and the corresponding self-interference problem related to the potential desensitization of the devices own receiver is highlighted. Then technical solutions to mitigate the self-interference at the RX band due to a nonlinear PA in the transmitter chain are reviewed, with specific emphasis on digital self-interference cancellation methods. As demonstrated through simulation and actual RF measurement examples, the cancellation solutions can substantially mitigate the RX desensitization problem, thus relaxing the RF isolation requirements between the TX and RX chains. Such cancellation methods are one potential enabling technique toward the full exploitation of the fragmented RF spectrum and the CA technology in future LTE-Advanced and beyond mobile networks.

Multirate Charge-Domain Filter Design for RF-Sampling Multi-Standard Receiver

This paper proposes a reconfigurable decimator architecture for a multi-standard receiver front-end. This architecture is based on direct radio-frequency bandpass sampling and analog discrete-time multirate signal processing. The overall front-end consists of a low-noise amplifier followed by a tunable charge-domain sampler, a reconfigurable decimator, and an analog-to-digital converter. The proposed decimator is constructed as a cascade of four switched-capacitor filtering stages. The frequency responses and the decimation factors of these stages are digitally controllable thus enabling high reconfigurability. The advantages of the proposed design are a high image rejection, a low overall implementation complexity, and high flexibility. The feasibility of the design is evaluated by computer simulations.