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Dive into the research topics where Victor Demjanenko is active.

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Featured researches published by Victor Demjanenko.


IEEE Computer | 1992

Postal address block location in real time

Paul W. Palumbo; Sargur N. Srihari; Jung Soh; Ramalingam Sridhar; Victor Demjanenko

The CEDAR real-time address block location system, which determines candidates for the location of the destination address from a scanned mail piece image, is described. For each candidate destination address block (DAB), the address block location (ABL) system determines the line segmentation, global orientation, block skew, an indication of whether the address appears to be handwritten or machine printed, and a value indicating the degree of confidence that the block actually contains the destination address. With 20-MHz Sparc processors, the average time per mail piece for the combined hardware and software system components is 0.210 seconds. The system located 89.0% of the addresses as the top choice. Recent developments in the system include the use of a top-down segmentation tool, address syntax analysis using only connected component data, and improvements to the segmentation refinement routines. This has increased top choice performance to 91.4%.<<ETX>>


IEEE Journal of Solid-state Circuits | 1992

A special-purpose content addressable memory chip for real-time image processing

Yong-Chul Shin; Ramalingam Sridhar; Victor Demjanenko; Paul W. Palumbo; Sargur N. Srihari

An application specific integrated circuit (ASIC) using a special-purpose content addressable memory that performs parallel search and multiple update (PSMU) operation is presented. This chip, referred to as multiple update content addressable memory (MUCAM), can search 256, 8-b-wide locations in parallel for target data and update all such locations with new data within 50 ns. MUCAM has been developed for image component labeling and merging operation in a connected component analyzer. It was fabricated using 0.9- mu m CMOS technology. >


Image and Vision Computing | 1990

Adjacency algorithms for linear octree nodes

Djaffer Ibaroudene; Victor Demjanenko; Raj S. Acharya

Abstract A formula for deriving the rectangular coordinates X, Y and Z from the octal locational code of a linear octree node is introduced. This formula is simpler than those that have previously been proposed1. Algorithms for determining the octal locational code of a face, edge and corner adjacent block to a given linear octree node are proposed. The edge and the corner adjacency algorithms are presented as direction extensions of the eastern, western, front, back, southern and northern neighbour finding procedures. Necessary and sufficient conditions for two octree nodes to be face adjacent in any of the above named directions are formulated in a form of digit tests on their respective locational codes. The face adjacency conditions derived in this paper were later used to select the octal value of the rightmost digit that must be appended or deleted from the locational code of the same size neighbour to identify smaller or larger size neighbours of a selected node in the specified direction. All the adjacency algorithms presented have a computational complexity of O(n), where n is the number of digits that form the locational code of the octree node for which a neighbour is sought.


machine vision applications | 1992

Contrast Enhancement of Mail Piece Images

Yong-Chul Shin; Ramalingam Sridhar; Victor Demjanenko; Paul W. Palumbo; Jonathan J. Hull

A New approach to contrast enhancement of mail piece images is presented. The contrast enhancement is used as a preprocessing step in the real-time address block location (RT-ABL) system. The RT-ABL system processes a stream of mail piece images and locates destination address blocks. Most of the mail pieces (classified into letters) show high contrast between background and foreground. As an extreme case, however, the seasonal greeting cards usually use colored envelopes which results in reduced contrast osured by an error rate by using a linear distributed associative memory (DAM). The DAM is trained to recognize the spectra of three classes of images: with high, medium, and low OCR error rates. The DAM is not forced to make a classification every time. It is allowed to reject as unknown a spectrum presented that does not closely resemble any that has been stored in the DAM. The DAM was fairly accurate with noisy images but conservative (i.e., rejected several text images as unknowns) when there was little ground and foreground degradations without affecting the nondegraded images. This approach provides local enhancement which adapts to local features. In order to simplify the computation of A and (sigma) , dynamic programming technique is used. Implementation details, performance, and the results on test images are presented in this paper.


international conference on asic | 1991

Special purpose register array for real-time image processing

Yong-Chul Shin; Ramalingam Sridhar; Victor Demjanenko; Paul W. Palumbo; Sargur N. Srihari

An ASIC which implements a special purpose register array for real-time application has been presented. This chip, referred to as MUCAM, performs parallel searches and multiple updates of up to 256 8-bit data within 52 ns. MUCAM has been developed for image component labeling, and merge operation in a connected component analyzer. It has been fabricated using 0.9 mu m CMOS technology.<<ETX>>


international conference on asic | 1992

Image processing ASIC for real-time contrast enhancement

Yong-Chul Shin; Ramalingam Sridhar; Victor Demjanenko; Paul W. Palumbo; Jonathan J. Hull; Sargur N. Srihari

An ASIC chip set that implements adaptive local contrast enhancement for real-time image processing is presented. The contrast enhancement is based on a nonlinear mapping M(A, sigma ,P), where A is an average, sigma is a standard deviation, and P is a center pixel over a 9*9 window. The throughput rate is 100 ns per pixel. A dynamic programming technique and pipelining are used to minimize the space-time constraint in the implementation.<<ETX>>


military communications conference | 1987

Simulation of a Distributed Communications Network using a Multi-tasking Uniprocessor

Victor Demjanenko; Michael L. Craner

A simulator was implemented for the emulation of N nodes in a distributed, adaptive satellite communications network with point-to-point communication links. The simulator provides programmability of node functions by acting as an interpreter for a simulation specific command language. A methodology for handling distributed updating of routing information and synchronization and scaling of event timelines is demonstrated. The simulator was written using YACC and C under UNIX and uses multiple processes and a file-based interprocess communications system. Experimental development was also performed under Concurrent C which looks promising but requires a more debugged Concurrent C implementation.


Archive | 1994

Local adaptive contrast enhancement

Yong-Chul Shin; Ramalingam Sridhar; Sargur N. Srihari; Victor Demjanenko


Archive | 1994

Global threshold method and apparatus

Dipankar Talukdar; Ramalingam Sridhar; Victor Demjanenko


Archive | 1992

Digital data memory unit and memory unit array

Yong-Chul Shin; Ramalingam Sridhar; Victor Demjanenko; Paul W. Palumbo; Sargur N. Srihari

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Paul W. Palumbo

State University of New York System

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Yong-Chul Shin

State University of New York System

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Dipankar Talukdar

State University of New York System

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Jung Soh

State University of New York System

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