Victor M. Goulart Ferreira

NSP: a Neuro---Symbolic Processor

This paper presents an implementation methodology of weighted ANNs whose weights have already been computed. The validation of this technique is made through the synthesis of circuits implementing the behaviour of specialised ANNs compiled from sets of logical clauses describing different logical problems. ANeuro---Symbolic Language (NSL) and its compiler5have been designed and implemented in order to translate the neural representation of a given logical problem into the corresponding VHDL code, which in turn can set devices such as FPGA(Field Programmable Gate Array). The result of this operation leads to an electronic circuit called NSP (Neuro---Symbolic Processor) that effectively implements a massively parallel interpreter of logic programs.

REDEFIS: a system with a redefinable instruction set processor

The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight performance or power constraints, or too complex to design in short TAT/TTM. REDEFIS is a HW/SW design platform for high level, efficient implementation of ASIPs/engines for SoC systems. It is composed of a reconfigurable instruction-set processor, capable to redefine its ISA according to the user application written in high level C language, and a set of design tools (an ISA Generator and a retargetable compiler). These processors can be used as flexible engines in embedded MPSoC systems, where its ISA is fully customized and design is done at high level C (no HDL writing is necessary). In this paper we present the Redefis design platform and an implementation of our dynamically reconfigurable ISA processor (codename Vulcan). Our results demonstrate the effectiveness of the system for encryption and bitwise applications.