Lovic Gauthier

Component-based design approach for multicore SoCs

This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. Component-based design provides primitives to build complex architectures from basic components. This bottom-up approach allows design-architects to explore efficient custom solutions with best performances. This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. The system specifications are represented as a virtual architecture described in a SystemC-like model and annotated with a set of configuration parameters. Our component-based design environment provides automatic wrapper-generation tools able to synthesize hardware interfaces, device drivers, and operating systems that implement a high-level interconnect API. This approach, experimented over a VDSL system, shows a drastic design time reduction without any significant efficiency loss in the final circuit.

Multiprocessor SoC platforms: a component-based design approach

A high-level, component-based methodology and design environment for multiprocessor SoC architectures reduces design time without significant efficiency loss in the final circuit. This design environment provides tools for automatic wrapper generation that synthesize hardware interfaces, device drivers, and operating systems implementing high-level interconnect APIs.

Automatic generation and targeting of application specific operating systems and embedded systems software

We propose a method of automatic generation of application specific operating systems (OSs) and automatic targeting of application software. OS generation starts from a very small bur yet flexible OS kernel. OS services, which are specific to the application and deduced from dependencies between services, are added to the kernel to construct the whole OS. Communication and synchronization functions in the application code are adapted to the generated OS. As a preliminary experiment, we applied the proposed method to a system example called token ring system.

Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design

To enable fast and accurate evaluation of HW/SW implementation choices of on-chip communication, we present a method to automatically generate timed OS simulation models. The method generates the OS simulation models with the simulation environment as a virtual processor Since the generated OS simulation models use final OS code, the presented method can mitigate the OS code equivalence problem. The generated model also simulates different types of processor exceptions. This approach provides two orders of magnitude higher simulation speedup compared to the simulation using instruction set simulators for SW simulation.

Automatic generation and targeting of application-specific operating systems and embedded systems software

Software (SW) parts become crucial in embedded systems. Operating systems (OSs) are often used to handle SW concurrency and communication. We propose a method of automatic generation of application-specific OSs and automatic targeting of application SW. OS generation starts from a very small, but yet flexible OS kernel. OS services, which are specific to the application and deduced from dependencies created by the system specification, are added to the kernel to construct the whole OS. Communication and synchronization functions in the application code are adapted to the generated OS. As experiments, we applied the proposed method to two system examples: a token-ring system and a very high data-rate digital subscriber line framer.

Colif: A design representation for application-specific multiprocessor SOCs

By separating component behavior and communication infrastructure and spanning multiple abstraction levels, Colif lets designers use a divide-and-conquer approach for complex designs and focus on important customizations as they progressively refine the SOC architecture.

Object-based hardware/software component interconnection model for interface design in system-on-a-chip circuits

The design of system-on-a-chip (SoC) circuits requires the integration of complex hardware/software components that are customized to efficiently execute a specific application. Nowadays, these components include many different embedded processors executing concurrent software tasks. In this paper, we present an object-based component interconnection model to represent both hardware and software components within a system architecture in a very high level of abstraction. This model is used in a design flow for automatic generation of hardware/software interfaces for SoC circuits. Design tools for automatic generation of embedded operating systems, hardware interfaces and associated device drivers are presented and evaluated using the results obtained with a VDSL application.

Colif: A multilevel design representation for application-specific multiprocessor system-on-chip design

Application-specific multiprocessor system-on-chip is required for high-volume future embedded systems. However, obtaining a good application-specific architecture could be an overly complex problem if we consider all the possible customizations. In this paper, we present Colif, a design representation that clearly separates component behavior and communication infrastructure. In addition, it has a flexible communication model that spans multiple abstraction levels. These features are suitable for a design flow where customizing communications and component behaviors at different abstraction levels are the central issue. The paper introduces the main concepts of Colif and compares it to existing system modeling approaches.

Application-specific multiprocessor Systems-on-Chip

It often happens that designers have to integrate different instruction-set processors on a single chip. Typical applications are wireless, image processing, xDSL, network and game processors. This paper deals with the three main problems that make the design of application-specific heterogeneous multiprocessor System-on-Chip very hard and expensive: higher level specifications; software support packages design; on-chip HW/SW communication design.

Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication

To fast evaluate HW/SW implementation of multiprocessor SoC communication, we present a method to simulate operating systems (OSs) on a simulation host without running instruction set simulators and generic OS simulation models. The method enables fast timed OS simulation including the preemption of task execution. Together with the fast simulation of synthesizable HW code (e.g. in synthesizable C), it will enable fast evaluation of HW/SW implementation of multiprocessor SoC communication.