Victor V. Zhirnov

Electron field emission for ultrananocrystalline diamond films

Ultrananocrystalline diamond (UNCD) films 0.1–2.4 μm thick were conformally deposited on sharp single Si microtip emitters, using microwave CH4–Ar plasma-enhanced chemical vapor deposition in combination with a dielectrophoretic seeding process. Field-emission studies exhibited stable, extremely high (60–100 μA/tip) emission current, with little variation in threshold fields as a function of film thickness or Si tip radius. The electron emission properties of high aspect ratio Si microtips, coated with diamond using the hot filament chemical vapor deposition (HFCVD) process were found to be very different from those of the UNCD-coated tips. For the HFCVD process, there is a strong dependence of the emission threshold on both the diamond coating thickness and Si tip radius. Quantum photoyield measurements of the UNCD films revealed that these films have an enhanced density of states within the bulk diamond band gap that is correlated with a reduction in the threshold field for electron emission. In additio...

Extending the road beyond CMOS

The accelerating pace of CMOS scaling is rapidly approaching the fundamental limits of MOSFET performance, even as the projected size of a high-performance and manufacturable MOSFET technology is currently being extended with growing confidence to the 22-nm node (featuring a 9-nm physical gate length). The new 2001 International Technology Roadmap for Semiconductors currently projects the industry to reach this node in 2016. However, this forecast assumes the traditional industry node-cycle cadence of a quadrupling of the number of transistors every three years for DRAMS and a return to the three-year cycle in 2004 for MPUs and ASICs. During the past several years the node cycles for MPUs have been accelerated to occur within two-year periods. This pace will bring the microelectronics industry to the end of silicon CMOS technology scaling sometime not later than 2016, and maybe as soon as 2010. The new Emerging Technologies section of the 2001 ITRS offers guidance on both sides of this problem: nanoelectronics for memory, logic, and information-processing architectures could possibly extend the time frame of the ITRS beyond CMOS.

Science and Engineering Beyond Moore's Law

In this paper, the historical effects and benefits of Moores law for semiconductor technologies are reviewed, and it is offered that the rapid learning curve obtained to the benefit of society by feature size scaling might be continued in several different ways. The problem is that as features approach the range of a few nanometers, electron-based devices depart radically from the ideal switch and, in fact, become very leaky in the off state. It is argued that there are some short-term solutions involving more highly parallel manufacturing, increased design efficiency, and lower cost packaging technologies that could continue the steep learning curve for cost reductions that have historically been achieved via Moores Law scaling. Another alternative might be to increase chip functionality by integrating devices that offer broadened chip functionality including, e.g., sensors, energy sources, oscillators, etc. A third alternative would be to invent an entirely new information processing state variable based on different physics, using electron spin, magnetic dipoles, photons, etc., to improve the performance and reduce switching energy for devices whose smallest features are on the order of a few nanometers. Each of these alternatives is being actively explored and an overview of each strategy and progress to date is given in the paper. A final alternative offered in the paper is to learn from information processing examples in nature, specifically in living systems. An E.coli cell of about one cubic micrometer volume is shown to be an incredibly powerful and energy-efficient information processor relative to the performance of an end-of-scaling silicon processor of the same volume. The paper concludes by pointing out some of the crucial differences between E.coli information processing and conventional approaches with the hope technologies can be invented using the hints offered by biosystems.

Scaling limits of resistive memories.

This paper is intended to provide an expository, physics-based, framework for the estimation of the performance potential and physical scaling limits of resistive memory. The approach taken seeks to provide physical insights into those parameters and physical effects that define device performance and scaling properties. The mechanisms of resistive switching are based on atomic rearrangements in a material. The three model cases are: (1) formation of a continuous conductive path between two electrodes within an insulating matrix, (2) formation of a discontinuous path of conductive atoms between two electrodes within an insulating matrix and (3) rearrangement of charged defects/impurities near the interface between the semiconductor matrix and an electrode, resulting in contact resistance changes. The authors argue that these three model mechanisms or their combinations are representative of the operation of all known resistive memories. The central question addressed in this paper is: what is the smallest volume of matter needed for resistive memory? The two related tasks explored in this paper are: (i) resistance changes due to addition or removal of a few atoms and (ii) stability of a few-atom system.

New frontiers: self-assembly and nanoelectronics

In the quest for new semiconductor materials and processes, researchers focus on self-assembly, a concept that draws from diverse disciplines like chemistry, biology, material science, and electrical engineering. The following areas are examined: information theory; thermodynamics, synergetics and self-assembly; ribosome based lithography; nanofabrication by self-assembly; molecular electronics; and smart matter.

Voltage-time dilemma of pure electronic mechanisms in resistive switching memory cells

Metal/insulator/metal thin film stacks showing stable resistive switching are promising candidates for future use as a nonvolatile resistive random access memory, competitive to FLASH and DRAM. Although the switching mechanisms are not completely understood a lot of theories and models try to describe the effects. One of them postulates the trapping and detrapping of electronic charge in immobile traps as the reason for the resistance changes, also known as Simmons & Verderber model. This contribution shows that this “pure electronic” switching mechanism will face a voltage-time dilemma—general to all switching insulators—at conditions competitive to the state-of-the-art FLASH. There is an incompatibility between the long retention time (10 years) and the short READ/WRITE current pulses (tREAD/WRITE≤100 ns) at high densities (area≤100×100 nm2) at low applied voltages (≤1 V). This general dilemma is exemplified in two detailed scenarios with different electronic band and defect properties.

Memory Devices: Energy–Space–Time Tradeoffs

Many memory candidates based on beyond complementary metal-oxide-semiconductor (CMOS) nanoelectronics have been proposed, but no clear successor has yet been identified. In this paper, we offer a methodology for system-level analysis and address the relationship of the maximum performance of a given memory device type to device physics. The method is illustrated for the classical dynamic RAM (DRAM) device and for the emerging memory device known as the resistive RAM (ReRAM).

Emerging Nanoscale Memory and Logic Devices: A Critical Assessment

This article presents the ERD Working Groups collective judgment with respect to the long-term potential of nanoscale memory and logic devices to replace silicon-based CMOS logic or baseline memory technology. It does not judge their potential to supplement or complement CMOS. The intent is thus prescriptive, not prescriptive: to provide a technically grounded, objective benchmark for emerging research memory and logic devices.

“Standardization” of field emission measurements

Interest in field emission and field emission devices has been renewed in the last 5 yr. This increase has been due to work on several new materials systems, which have shown promising field emission (FE) behavior. In turn, this interest gives impetus to the search for new FE sources. In order to move the technology ahead at a faster pace, there is a need for common ground rules and a “standardization” of the data reported so that it can be compared directly in a meaningful way and thereby accelerate the development process. In this article key factors affecting the FE data will be discussed and several parameters are suggested to initiate the process of developing a set of “standardized” FE parameters. A correct, or at least consistent, determination of characteristics such as work function, emission area, and field enhancement form the basis for developing a framework to make meaningful comparisons between different sets of data.

Boolean Logic and Alternative Information-Processing Devices

Emerging research device technologies might first appear in special applications that can extend conventional general-purpose processors along one of several axes. These applications could optimize the performance of future workloads such as recognition, mining, and synthesis by using the unique nonlinear output characteristics associated with the emerging research devices. However, a new device technology might emerge that, by way of first supplementing conventionally scaled CMOS, could eventually offer a highly scalable new information- processing paradigm.