Ralph K. Cavin

Limits to binary logic switch scaling - a gedanken model

In this paper we consider device scaling and speed limitations on irreversible von Neumann computing that are derived from the requirement of least energy computation. We consider computational systems whose material realizations utilize electrons and energy barriers to represent and manipulate their binary representations of state.

Science and Engineering Beyond Moore's Law

In this paper, the historical effects and benefits of Moores law for semiconductor technologies are reviewed, and it is offered that the rapid learning curve obtained to the benefit of society by feature size scaling might be continued in several different ways. The problem is that as features approach the range of a few nanometers, electron-based devices depart radically from the ideal switch and, in fact, become very leaky in the off state. It is argued that there are some short-term solutions involving more highly parallel manufacturing, increased design efficiency, and lower cost packaging technologies that could continue the steep learning curve for cost reductions that have historically been achieved via Moores Law scaling. Another alternative might be to increase chip functionality by integrating devices that offer broadened chip functionality including, e.g., sensors, energy sources, oscillators, etc. A third alternative would be to invent an entirely new information processing state variable based on different physics, using electron spin, magnetic dipoles, photons, etc., to improve the performance and reduce switching energy for devices whose smallest features are on the order of a few nanometers. Each of these alternatives is being actively explored and an overview of each strategy and progress to date is given in the paper. A final alternative offered in the paper is to learn from information processing examples in nature, specifically in living systems. An E.coli cell of about one cubic micrometer volume is shown to be an incredibly powerful and energy-efficient information processor relative to the performance of an end-of-scaling silicon processor of the same volume. The paper concludes by pointing out some of the crucial differences between E.coli information processing and conventional approaches with the hope technologies can be invented using the hints offered by biosystems.

Wave Pipelining: Theory and CMOS Implementation

List of Figures. List of Tables. Preface. 1. Introduction and Motivation. 2. Clock Period Constraints: Single Stage Systems. 3. Clock Period Constraints: Multiple Stage Systems. 4. Exact Timing Analysis. 5. Exact Timing Analysis: Algorithm. 6. Practical Considerations in Wave Pipelining. 7. Design Examples. 8. Conclusions. A: Example Model File. B: Calculation of Tolerance of Parametric Variations. References. Index.

A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

This paper describes an adaptive bandwidth bus (ABB) architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode signaling. Attaining a maximum aggregate bandwidth of 16 Gb/s (i.e., 1 Gb/s per line) across lossy on-chip interconnects spanning 1.75 cm in length, the bus core fabricated in 0.35 /spl mu/m CMOS technology dissipates approximately 93 mW with a supply of 2.5 V and signal activity of 0.5, equivalent to 5.71 pJ/bit. Experimental results using a 16-bit reference bus design that can be externally programmed to operate in voltage, current or adaptive modes indicate a 50% reduction in power dissipation over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltage-mode (VM) sensing, respectively.

Future Microsystems for Information Processing: Limits and Lessons From the Living Systems

The paper examines the impact of the physics of extremely scaled information processing devices and systems, with a focus on energy minimization. Architectural implications are also discussed including the impact on system scaling. In order to comprehend the system-level scaling and performance limits, understanding of limiting behavior for many electronic components is needed, e.g., logic and memory devices, I/Os, communication, etc. In the second part of the paper, entirely new information processing concepts are discussed based on learning from examples in nature, specifically, the individual living cell will be considered in the context of information processing. In the paper, a bacterial cell, such as E.coli of about one cubic micrometer volume is shown to be a very efficient and powerful information processor, far surpassing conceivable performance in the same volume by an ultimately scaled semiconductor system. Advances in the science of synthetic biology are beginning to suggest possible pathways for future information processing technologies. It might be possible that some of the physical limits faced by semiconductor technology may in fact be overcome by borrowing from synthetic biology principles.

A 16Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

An adaptive bandwidth bus (ABB) uses both current and voltage sensing techniques to improve interconnection delay and signaling bandwidth compared to conventional static busses. Attaining a maximum aggregate bandwidth of 16Gb/s (i.e. 1Gb/s per line) across lossy on-chip interconnects spanning 1.75cm in length, the bus core fabricated in TSMC 0.35 /spl mu/m CMOS technology dissipates approximately 93mW with a supply of 2.5V and signal activity of 0.5. Experimental results indicate a reduction in power of 50% over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltage-mode (VM) sensing, respectively.

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-/spl mu/m Bulk CMOS indicates a reduction in power dissipation of approximately 62% over CM sensing and an increase in maximum data rate of 40% over voltage-mode signaling.

Low-power design methodology for an on-chip bus with adaptive bandwidth capability

This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achieves high data transmission rates while minimizing the number of repeaters by nearly 1/3. The technique uses low-impedance current-mode sensing to increase the data throughput and minimizes the static power dissipation inherent to current-mode signaling by adaptively changing the interconnection bandwidth given a change in input signal activity. Since bandwidth is related to power dissipation, the adaptive bus attains energy efficient data transmission by expending minimum power required to support the bus signal activity. The design method is based on statistical analysis of address streams extracted for typical benchmark programs using a microprocessor time-based simulator in combination with circuit-level power analysis. Simulation results indicate improvements in power dissipation of up to 65% and 40% over current and voltage mode signaling schemes, respectively.

Design of integrated circuits: directions and challenges

Several of the dimensions of IC CAE technology are discussed, focusing on two design styles: custom design, used for commodity products such as DRAMs, microprocessors, etc., where large volume production is planned and area reduction and performance maximization can be expected to return large dividends; and the design of application-specific integrated circuits (ASICs), utilizing either very regular, prepatterned silicon arrays customized at the interconnect level or predesigned, parameterized libraries of cells that are usually arranged in rows and interconnected. The design research that will be required in order to attain the objectives of highly automated design systems and shorter product design cycles for integrated circuits are outlined. Metrics for design system performance are discussed. >

A semiconductor industry perspective on future directions in ECE education

This paper looks at changes in the education of engineers made necessary by unprecedented challenges within the semiconductor industry, from the perspective of a not-for-profit consortium of semiconductor manufacturers. To design and implement curricula to serve as a basis for the 40-year career of engineering graduates is a daunting challenge in this rapidly evolving environment. The authors propose ten principles that should be of use in connecting the graduates of today with the engineering careers of tomorrow.