Victor Varshavsky

Logical timing (global synchronization of asynchronous arrays)

The problem of global synchronization is solved for asynchronous processor arrays and multiprocessor systems with an arbitrary interconnection graph. Global synchronization of asynchronous systems is treated as a homomorphic mapping of an asynchronous system behavior in logical time onto the behavior of the corresponding synchronous system with a common clock functioning in physical time. The solution is based on decomposing the system to the processor stratum and synchro-stratum; the latter plays the role of a global asynchronous clock. For the case of a synchronous system with two-phase master-slave synchronization, a simple implementation of the synchro-stratum for the corresponding asynchronous system is proposed. It is shown that, depending on the local behavior of the processors, the synchro-stratum is able to perform two types of global synchronization: parallel synchronization and synchronization that uses a system of synchro-waves.<<ETX>>

Analysis and identification of speed-independent circuits on an event model

The object of this article is the analysis of asynchronous circuits for speed independence or delay insensitivity. The circuits are specified as a netlist of logic functions describing the components. The analysis is based on a derivation of an event specification of the circuit behavior in a form of a signal graph. Signal graphs can be viewed either as a formalization of timing diagrams, or as a signal interpreted version of marked graphs (a subclass of Petri nets). The main advantage of this method is that a state explosion is avoided. A restoration of an event specification of a circuit also helps to solve the behavior identification problem, i.e., to compare the obtained specification with the desired specification. We illustrate the method by means of some examples.

GALA (Globally Asynchronous - Locally Arbitrary) Design

The problem of organizing the temporal behavior of digital systems is discussed. This problem is mainly associated with providing the interface between physical (natural) and logical (artificial) time. The most common method of interfacing is based on a system clock that removes physical time from the behavior models A number of algorithms that can be easily formulated in logical time present a great difficulty in the asynchronous case. The suggested GALA (Globally Asynchronous - Locally Arbitrary) design methodology is based on decomposing the system to a Processors Stratum and a Synchro-Stratum. The synchro-stratum acts as a distributed asynchronous clock that produces local synchro-signals for the processor stratum, which is basically a synchronous prototype. A synchro-stratum, like any asynchronous circuit, interacts with the external devices, including the processor stratum, by handshake. Every local device produces an acknowledgment signal and sends it to the synchro-stratum. The designer can use a wide range of methods to implement this signal (Locally Arbitrary): from a self-timed design to a built-in parallel delay. For various disciplines of prototype clocking, corresponding synchro-stratum implementations are suggested. The GALA methodology is illustrated on several design examples, such as a counter with constant response time, one-two-one track FiFo, arbitration-free counterflow processor architecture.

Asynchronous Control Device Design by Net Model Behavior Simulation

We discuss the problem of designing asynchronous control devices for discrete event coordination specified by a Petri net model. The design is based on the compilation of standard circuit modules corresponding to PN fragments into a net modeling PN behavior and on the semantic interpretation of the modeling circuit. The impossibility of asynchronous implementation of the indivisible operation of marking change at the circuit level leads to the necessity of modeling PN with modified rules of marking change. Modifications of the known modules, a number of new module types, the rules of the module connections, and the procedures of minimization are given that considerably improve the quality of the obtained solutions in terms of both speed and area. The design “reefs” are fixed. The minimization procedures are usually associated with a change of marking change rules producing the problems of providing the equivalence of the initial and modified PNs.

SELF-TIMING-tools for hardware support of parallel, concurrent and event-driven process control

After describing the main idea of self-timing, the authors consider the advantages and costs of the application of self-timing. They discuss the synchronisation of processes in self-timed systems.<<ETX>>

Beta-CMOS artificial neuron and implementability limits

The paper is focused on the functional possibilities (class of representable threshold functions), parameter stability and learnability of the artificial learnable neuron implemented on the base of CMOS β-driven threshold element. A neuron β-comparator circuit is suggested with a very high sensitivity to input current change that allows us to sharply increase the threshold value of the functions. The SPICE simulation results confirm that the neuron is learnable to realize threshold functions of 10, 11 and 12 variables with maximum values of threshold 89, 144 and 233 respectively. A number of experiments were conducted to determine the limits in which the working parameters of the neuron can change providing its stable functioning after learning to the functions for each of these threshold values. MOSIS BSIM3v3.1 0.8μm transistor models were used in the SPICE simulation.

Learning Experiments with CMOS Artificial Neuron

One of the key problems in designing analog/digital implementations of artificial neuron is the problem of its limiting functional power, i.e. the question about what class of threshold function the neuron can be taught to produce. In problems of this kind, the class of threshold functions is determined by a certain criterion of complexity, for example, number of variables, sum of input weights (as for vCMOS neuron [1,2]), maximum threshold (as for β-driven CMOS neuron [3,4]), etc.

Beta-CMOS implementation of an artificial neuron

The improved version of digital-analog CMOS implementation of an artificial neuron is discussed. This neuron is learnable to logical threshold functions, being functionally powerful and highly noise-stable. It is built on the basis of a previously suggested circuit consisting of synapses, (beta) -comparator and output amplifier. Every learnable synapse contains 5 minimum transistors and a capacitor for storing the results of the learning. It has been shown that higher non-linearity of the (beta) -comparator in the threshold zone can sharply increase the threshold of the realized functions and noise- stability of the neuron. To increase the minimum leap of voltage at the (beta) -comparator output in the threshold zone which is attainable during the teaching, it is suggested to use an output amplifier with threshold hysteresis. For this aim, the neuron has three output amplifiers with different thresholds. The output of the amplifier with the middle value of threshold is the output of the neuron; the outputs of the other two amplifiers are used during the teaching. The way is suggested of refreshing the voltages (found during the teaching) on the capacitors during the evaluation process. The results of SPICE simulation prove that the neuron is learnable to most complicated threshold functions of 10 and more variables and that it is capable to maintain the learned state for a long time. In the simulation, transistor modes MOSIS BSIM3v3.1 0.8 micrometer were used.

Designing self-timed devices using the finite automaton model

The authors suggest a procedure for designing a self-timed device defined by the finite automaton model. This procedure proves useful when designing these devices using the available synchronous behavior specifications. They illustrate the effectiveness of their procedure by applying it to the design of a stack memory and constant acknowledgement delay counter. >

GALA approach in design of asynchronous control for counterflow pipeline processor

This paper approaches the problem of building an asynchronous control for a stage of the Sproulls Counterflow Pipeline Processor (CFPP) that does not need arbiters. It is shown that there is no arbitration situations in a synchronous pipeline control circuit with two-track synchronization. An asynchronous control circuit can be built by a synchronous prototype with help of GALA-methodology using the procedure of synchro-stratum designing suggested earlier by the authors [1994-6].