Michael Kishinevsky

Basic Gate Implementation of Speed-Independendent Circuits

Existing methods for synthesis of speedindependent circuits under unbounded delay model have difficulties in combining the generality of formal approach with the practicality of the implementation architectures used at the logic level. This paper presents a characteristic property of the state graph specification, called Monotonous Cover requirement, implying its hazard-free implementation within the standard structure of a two-level SOP logic and a row of latches. The overall synthesis procedure ensures satisfiability of this condition by applying the generalised state assignment approach.

Performance Analysis Based on Timing Simulation

Determining the cycle time and a critical cycle is a fundamental problem in the analysis of concurrent systems. We solve this problemusing timing simulation of an underlying Signal Graph (an extension of Marked Graphs). For a Signal Graph with n vertices and m arcs our algorithm has the polynomial time complexity O(b/sup 2/m), where b is the number of vertices with initially marked in-arcs (typically b≪n). The algorithm has a clear semantic and a low descriptive complexity. We illustrate the use of the algorithm by applying it to performance analysis of asynchronous circuits.

OR Causality: Modelling and Hardware Implementation

Asynchronous circuits behave like concurrent programs implemented in hardware logic. The processes in such circuits are synchronised in accordance with the dynamic logical and causal conditions between switching events. In this paper we investigate a paradigm called OR causality. Petri nets and Change Diagrams provide adequate modelling and circuit synthesis tools for the various OR causality types, yet they do not always bring the specifier to a unique decision about which modelling construct must be used for which type. We present a unified descriptive tool, called Causal Logic Net, which is graphically based on Petri net but has an explicit logic causality annotation for transitions. The signal-transition interpretation of this tool is analogous to, but more powerful than, the well-known Signal Transition Graph. A number of examples demonstrate the usefulness of this model in the synthesis of asynchronous control circuits.

Specification and analysis of self-timed circuits

The problems of self-timed behavior specification and verification are considered on the basis of an event model—Change Diagram (CD). The descriptive power of a CD model is demonstrated by comparing the CD with Signal Transition Graphs (STG). CD differs from STG by two types of causal relations (AND and OR) between events (in STG only AND-relation is presented). CD verification is shown to be reducible to an analysis of precedence and concurrency properties for events. These properties are hard to analyze directly by a cyclic CD. We suggest that the cyclic description be replaced by an equivalent acyclic one (called an unfolding) in order to solve the analysis problem. The notion of CD correctness is introduced, and the necessity and sufficiency of this notion for the implementation to be in self-timed class are shown. The polynomial algorithms for CD correctness verification are considered.

Automatic synthesis and optimization of partially specified asynchronous systemsProceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

A method for automating the synthesis of asynchronous control circuits from high level (CSP-like) and/or partial STG (involving only functionally critical events) specifications is presented. The method solves two key subtasks in this new, more flexible, design flow: handshake expansion, i.e. inserting reset events with maximum concurrency, and event reshuffling under interface and concurrency constraints, by means of concurrency reduction. In doing so, the algorithm optimizes the circuit both for size and performance. Experimental results show a significant increase in the solution space explored when compared to existing CSP-based or STG-based synthesis tools.

Change Diagram : A behavioural model for very speed VLSI circuit/highly parallel systems

The paper proposes a formal moded, named change diagram, for analysis and synthesis of the very high speed complex VLSI circuitslsystems. The CD allows f o r unambiguous expression of concurrent activities riot only of distributive processes, but also those of serni-modular. The equivalence of CDs and Petri Nets is investigated too. Possible usage of CDs in new generation simulators design is outlined. keywords : concurrency, Petri Nets, Change Diagram, self-timing, VLSI circuits/systems