Vijay Nath

A darlington pair transistor based operational amplifier

In this paper a new CMOS operational amplifier using a Darlington pair based gain boosted technique has been enunciated. The proposed Opamp shows high gain as well as high UGB using capacitor compensation technique and proper biasing circuit. It is operated on rail to rail power supply of ±900mV. This amplifier is highly useful for wireless communications due to low power consumption, high bandwidth, high gain and high noise immunity. The designed operational amplifier gain is 89dB, bandwidth is 4.40 GHz and phase margin is 67O, and slew rate is 991.6V/μS. This circuit is designed using Cadence analog & digital system design tools of gpdk45nm technology.

An Ultra Low Power CMOS RF Front-End-Based LNA and Mixer for GPS Application

In this research article, a 1.5-GHz low-noise amplifier and down-conversion double-balanced mixer have been designed for CMOS RF front receiver. It plays a vital role in Global Positioning System (GPS) for increasing the safety and efficiency of flight. Gilbert down-conversion topology has been adopted for the design of mixer, while single-differential topology with matching network has been implemented for low-noise amplifier. The conversion gain of the mixer is 16 dB, noise figure is 12 dB, IIP3 is −5.66 dBm, and 1-dB compression point is 1.369 dBm. The designed circuit is tested at 1.5 V, and the simulation has been carried out with the help of cadence analog design environment with UMC 90 nm technology.

IC Packaging: 3D IC Technology and Methods

The research article discusses the flow of product design helpful for semiconductor design companies. Chip-manufacturing industries are fabricating next-generation 3D IC and their packaging is the new challenge. The 3D packaging has low power dissipation, high density, high performance, and reliability. Microelectronics industries follow the 3D IC development based on the TSV technology, processing of micro-bumps, helpful for interconnecting the stacking chips. The reliability of 3D IC, using TSV interposer, is reviewed in detail for Xilinx FPGA environment. The flow and process of WoW stacking methodology followed by low temperature for TSV fabrication are also discussed. 3D interconnection technologies possess excellent reliability and applied for 3D integration in real-time applications and manufacturing. Cost, supply chains, and heat management are the challenges in 3D integration, and chip-package interaction (CPI) is also the reliability issue of 3D IC integration. To reduce the CPI, differential heating/cooling (H/C) chip-joining technique is also discussed, which effectively reduce fractures in ultra-low–k (ULK) Si chips.

An ultra low power and low phase noise current starved CMOS VCO for wireless application

In this article an ultra low power, low phase noise current starved CMOS VCO are proposed. This CSVCO is applicable for wireless communication such as in RFIC (Radio Frequency Integrated Circuits), wireless transceiver, clock generation and recovery, phase lock loop etc. This proposed circuits area and power consumptions are very less and compatible with wireless devices. It demonstrates the superlative performance of the CSVCO. Transient response and phase noise analysis is performed and after simulation the phase noise at 1MHz is -104.0dBc/Hz and power gain estimation at 2 GHz is -185.8dBm is obtained with supply voltage of 1 V. It is performed using cadence virtuoso gpdk045 nm CMOS technology.

Design of Smart Security Systems for Home Automation

With continuously increasing the use of energy and growth in population, conservation of energy is very much needed. Remote access to electronic appliances can solve the problem. Instructions can be given to these systems through a web or an android application. Some of the technologies which are used can be GSM, ZigBee, Wi-Fi, and Bluetooth, along with different controlling devices. This paper gives a survey of all those systems which have already been used in various different applications.

Study and Design of Smart Embedded System for Train Track Monitoring Using IoTs

Trains are a key and cheaper mode of transportation systems in most developed countries around the world. Nowadays, train derailment in India is a major problem, thousands of peoples are dying due to derailing accidents. Other major problems are collision. It is also often occurring and results in severe damage to life and property. This chapter presents a thought of smart train track monitoring system and collision using IoT methods. This chapter presents various innovative ideas to control and detect the cause of derailed systems such as the strength of track, vibration measurement, load measurement, track alignment, conditioning of track. In this proposed smart system, track conditions will be monitored by IoTs systems with the help of different smart sensors pasted in track and information of track will be delivered to nearby substations, drivers, and central railway monitoring office. Before passing of the trains, the track will be scanned by systems and after the green signal of the system, train will be allowed to run on the particular track. The proposed methods can reduce the accidents.

Design and Implementation of a Reaction Timer Using CMOS Logic

This paper presents an overview of a reaction timer having an accuracy up to two decimal places (which is extendable). Three decade counters constitute the circuitry of this reaction timer wherein each of the decade counters is connected to four master–slave J-K flip-flops to form a sequential circuit. A delay signal is also introduced at the input so that the output is genuine. The whole simulation process is carried out in Cadence virtuoso analog and digital design environment of gpdk045 nm CMOS technology at a supply voltage of 1 V.

Design Strategy for Smart Toll Gate Billing System

This paper expresses an overview of the design strategy of smart toll and billing collection system. Nowadays, due to an improved transportation infrastructure, a huge rush can be seen at the toll plazas in order to pay the toll taxes. Hence, an effective model for automation in toll tax payment is being designed so that the traffic at these toll plazas can be reduced. The so-called model uses a combination of an image capturing device with high-resolution processor which would not only reduce the monetary loss due to faults in manual operation but also save the time of the riders. The objective of the project is to design a layout which automatically identifies approaching vehicles, records the data related to the vehicles, and generates an appropriate toll bill which can be paid either in cash or using e-wallets, plastic money, or by providing a system for automatic deduction of the amount from a predefined user account. This vision when implemented would help to reduce traffic congestion at toll plazas and decrease the fuel consumption of vehicles waiting in the queue.

Electronic Toll Collection System Using Barcode Technology

This paper emphasizes the barcode technology for automatic Electronic Toll Collection (ETC) systems, in order to avoid the ever-increasing stream of traffic and the long queues at the tollbooths of the highways. The proposed techniques make use of digital image processing techniques to scan the barcode and to match it with the existing database, by utilizing the decoded data. The implemented hardware setup has been illustrated and discussed in detail. The proposed technique for barcode detection significantly improves the speed, efficiency and lowers the cost of implementation. The method has been implemented by using Python and OpenCV.

A High-Performance Energy-Efficient 75.17 dB Two-Stage Operational Amplifier

This paper discusses the design and analysis of two-stage CMOS operational amplifier. This design is operated at the supply of 1.5 V in 90 nm CMOS technology. In this design, 75.17 dB open-loop gain is achieved and having 7.73 MHz unity gain bandwidth and 148.8 m degree phase margin. This circuit has 10 pF capacitive load with 0.14 nW average power dissipation and slew rate is 0.25 V/μs. This proposed circuit is designed and simulated in cadence UMC 90 nm technology.