Vijaykrishnan Narayanan

Experimental Staggered-Source and N+ Pocket-Doped Channel III--V Tunnel Field-Effect Transistors and Their Scalabilities

In this paper, we experimentally demonstrate 100% enhancement in drive current (ION) over In0.53Ga0.47As n-channel homojunction tunnel field-effect transistor (TFET) by replacing In0.53Ga0.47As source with a moderately staggered and lattice-matched GaAs0.5Sb0.5. The enhancement is also compared with In0.53Ga0.47As N+ pocket (δ)-doped channel homojunction TFET. Utilizing calibrated numerical simulations, we extract the effective scaling length (λeff) for the double gate, thin-body configuration of the staggered heterojunction and δ-doped channel TFETs. The extracted λeff is shown to be lower than the geometrical scaling length, particularly in the highly staggered-source heterojunction TFET due to the reduced channel side component of the tunnel junction width, resulting in improved device scalability.

Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors

Heterogeneous multicores are envisioned to be a promising design paradigm to combat todays challenges of power, memory, and reliability walls that are impeding chip design using deep submicron technology. Future multicores are expected to integrate multiple different cores, including GPGPUs, custom accelerators and configurable cores. In this paper, we introduce an important dimension-technology-using which heterogeneity can be introduced in multicores to improve their energy-performance envelope. Specifically, we analyze the benefits of heterogenous technologies for processor cores and cache subsystems. We discuss two promising device candidates (Tunnel-FET and Magnetic-RAM) for introducing technological diversity in the multicores and analyze their integration in the processor and cache hierarchy in detail. Our analysis shows that introducing such a kind of heterogeneity can significantly enhance the performance and energy behavior of future multicore systems.

Rf-powered systems using steep-slope devices

Steep-slope tunnel devices promise new opportunities in ultra-low-power computing. This paper focuses on how steep-slope devices can enhance efficiencies of harvesting ambient RF energy and improve power efficiency of analog and digital computational blocks.

An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization

Biological vision systems use saliency-based visual attention mechanisms to limit higher-level vision processing on the most visually-salient subsets of an input image. Among several computational models that capture the visual-saliency in biological system, an information theoretic AIM(Attention based on Information Maximization) algorithm has been demonstrated to predict human gaze patterns better than other existing models. We present an FPGA based implementation of this computationally intensive AIM algorithm to support embedded vision applications. Our implementation provides performance of processing about 4M pixels/sec for 25 basis functions with a convolution kernel size of 21 by 21 for each of the R, G, and B color-channels, when implemented on a Virtex-6 LX240T. We also provide an optimization aimed at controlling the trade-off between power consumption and latency, and performance comparisons with a GPU implementation.

Automated mapping for reconfigurable single-electron transistor arrays

Reducing power consumption has become one of the primary challenges in chip design, and therefore significant efforts are being devoted to find holistic solutions on power reduction from the device level up to the system level. Among a plethora of low power devices that are being explored, single-electron transistors (SETs) at room temperature are particularly attractive. Although prior work has proposed a binary decision diagram-based reconfigurable logic architecture using SETs, it lacks an automated synthesis tool for the device. Consequently, in this work, we develop a product-term-based approach that synthesizes a logic circuit by mapping all its product terms into the SET architecture. The experimental results show the effectiveness and efficiency of the proposed approach on a set of MCNC benchmarks.

Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores

Energy-Delay-Product-aware DVFS is a widely-used technique that improves energy efficiency by dynamically adjusting the frequencies of cores. Further, for multithreaded applications, barrier-aware DVFS is a method that can dynamically tune the frequencies of cores to reduce barrier stall times and achieve higher energy efficiency. In both forms of DVFS, frequencies of cores are reduced from the maximum value to achieve better energy efficiency. TFET devices operate at energy efficiencies that cannot be achieved by CMOS devices. This advantage of TFET devices can be exploited in the context of multicore processors by replacing some of the CMOS cores with energy efficient TFET alternatives. However, the energy benefits of TFET devices are observed at relatively lower voltages, which results in a degradation in performance due to executing at lower frequencies. Although applications cannot be limited to run always at such lower frequencies, it can be significantly beneficial from an energy efficiency perspective to make use of energy efficient TFET cores during the times applications spend at these frequencies. In this paper, we show that due to EDP-aware DVFS and barrier-aware DVFS, multithreaded applications run for a significant portion of their execution time at frequencies at which TFET cores are more energy efficient. We further show that, at those frequencies, dynamically migrating threads to TFET cores can achieve average leakage and dynamic energy savings of 30% and 17%, respectively, with a performance degradation of less than 1%.

Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits

In this paper, we characterize the Energy-Delay performance of logic circuits realized using Single Electron Transistor (SET) devices. As technology scaling progresses, it is getting increasingly challenging to continue reducing energy, especially at low activity factors and low V CC , due to increasing leakage energy dominance. A SET can be viewed as the ultimate transistor operating in the limit of scaling; hence, we use this device as an example to understand the challenges of energy-reduction in the nanoscale. We explore the design space for SET-devices based on physical dimensions and electrostatic properties. Based on this design space, we characterize SETs into categories of applications: complementary-logic design, and BDD design with sense amplification. Based on these two circuit design styles, we compare the Energy-Delay products of benchmark logic circuits, implemented using nanometer CMOS and SETs.

Steep Slope Devices: Enabling New Architectural Paradigms

The existence of domains where traditional CMOS processors are inefficient has been well-documented in the current literature. In particular, the inefficiency of general purpose CMOS designs operating at very low supply voltages is well-known, and steep sub-threshold slope technologies, such as Tunneling Field Effect Transistors (TFETs), have been demonstrated as a viable alternative for the low-voltage operation domain. However, restricting the design space of steep slope technology-based processors to near-threshold or sub-threshold general purpose processors does the technology a disservice. Steep slope (SS) architectures can simultaneously expand the frontiers of viable computers at both ends of the energy scale: On the one hand, SS architectures enable ultra-low power sensor nodes and wearable technology, while on the other, they are applicable to high powered servers and high performance computing engines. We demonstrate the benefits of adapting this technology in such non-conventional domains, while attempting to address the major challenges encountered. We explore the effect of noise and variations at various levels of abstraction, ranging from the device to the architecture, and examine various techniques to overcome them.

Enabling Power-Efficient Designs with III-V Tunnel FETs

III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, uni-directional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level.

A hardware architecture for accelerating neuromorphic vision algorithms

Neuromorphic vision algorithms are biologically inspired algorithms that follow the processing that takes place in the visual cortex. These algorithms have proved to match classical computer vision algorithms in classification performance and even outperformed them in some instances. However, neuromorphic algorithms suffer from high complexity leading to poor execution times when running on general purpose processors, making them less attractive for real-time applications. FPGAs, on the other hand, have become true signal processing platforms due to their lightweight, low power consumption and massive parallel computational resources. This paper describes an FPGA-based hardware architecture that accelerates an object classification cortical model, HMAX. Compared to a CPU implementation, this hardware accelerator offers 23X (89X) speedup when mapped to a single-FPGA (multi-FPGA) platform, while maintaining a classification accuracy of 92.5%.