Huichu Liu

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

Steep switching tunnel FET: a promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications

Steep switching Tunnel FETs (TFET) can extend the supply voltage scaling with improved energy efficiency for both digital and analog/RF application. In this paper, recent approaches on III-V Tunnel FET device design, prototype device demonstration, modeling techniques and performance evaluations for digital and analog/RF application are discussed and compared to CMOS technology. The impact of steep switching, uni-directional conduction and negative differential resistance characteristics are explored from circuit design perspective. Circuit-level implementation such as III-V TFET based Adder and SRAM design shows significant improvement on energy efficiency and power reduction below 0.3V for digital application. The analog/RF metric evaluation is presented including gm/Ids metric, temperature sensitivity, parasitic impact and noise performance. TFETs exhibit promising performance for high frequency, high sensitivity and ultra-low power RF rectifier application.

Tunnel FET RF Rectifier Design for Energy Harvesting Applications

Radio-frequency (RF)-powered energy harvesting systems have offered new perspectives in various scientific and clinical applications such as health monitoring, bio-signal acquisition, and battery-less data-transceivers. In such applications, an RF rectifier with high sensitivity, high power conversion efficiency (PCE) is critical to enable the utilization of the ambient RF signal power. In this paper, we explore the high PCE advantage of the steep-slope III-V heterojunction tunnel field-effect transistor (HTFET) RF rectifiers over the Si FinFET baseline design for RF-powered battery-less systems. We investigate the device characteristics of HTFETs to improve the sensitivity and PCE of the RF rectifiers. Different topologies including the two-transistor (2-T) and four-transistor (4-T) complementary-HTFET designs, and the n-type HTFET-only designs are evaluated with design parameter optimizations to achieve high PCE and high sensitivity. The performance evaluation of the optimized 4-T cross-coupled HTFET rectifier has shown an over 50% PCE with an RF input power ranging from -40 dBm to -25 dBm, which significantly extends the RF input power range compared to the baseline Si FinFET design. A maximum PCE of 84% and 85% has been achieved in the proposed 4-T N-HTFET-only rectifier at -33.7 dBm input power and the 4-T cross-coupled HTFET rectifier at -34.5 dBm input power, respectively. The capability of obtaining a high PCE at a low RF input power range reveals the superiority of the HTFET RF rectifiers for battery-less energy harvesting applications.

Rf-powered systems using steep-slope devices

Steep-slope tunnel devices promise new opportunities in ultra-low-power computing. This paper focuses on how steep-slope devices can enhance efficiencies of harvesting ambient RF energy and improve power efficiency of analog and digital computational blocks.

Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective

Sea-level soft error performance has been investigated for Si FinFET, III-V FinFET and III-V Heterojunction Tunnel FET in this paper. Transient error generation and transient current profiles in these devices have been evaluated using device simulation. Based on the critical charge extraction for each emerging device-based circuit, the electrical and latching window masking effects have been studied. Below 0.5V, III-V FinFET logic shows reduced soft error rate (SER) compared to Si FinFET. HTFET shows reduced SER for both SRAM and logic compared to Si and III-V FinFET over the evaluated voltage range of 0.3V-0.6V.

Intrinsic electronic switching time in ultrathin epitaxial vanadium dioxide thin film

This letter investigates the intrinsic electronic switching time associated with the insulator-to-metal phase transition in epitaxial single crystal vanadium dioxide (VO2) thin films using impedance spectroscopy and ac conductivity measurements. The existence of insulating and metallic phase coexistence, intrinsic to the epitaxial (001) oriented VO2 thin film grown on a (001) rutile TiO2 substrate, results in a finite capacitance being associated with the VO2 films in their insulating phase that limits the electronic switching speed. Insights into the switching characteristics and their correlation to the transport mechanism in the light of phase coexistence are obtained by performing a detailed scaling study on VO2 two-terminal devices.

Electrical Noise in Heterojunction Interband Tunnel FETs

We present an analysis of electrical noise in III-V heterojunction TFET (HTFET). Using numerical simulations, random telegraph noise (RTN) amplitude induced by a single charge trap is investigated with regard to trap location, electron band-to-band-generation rate, bias, and transistor size. It is found that HTFET RTN amplitude does not scale inversely with gate length and is governed by tunneling distance of carriers at source-channel junction. HTFET exhibits 40% less relative RTN amplitude at 0.3 V at gate lengths around 20 nm, over subthreshold Si-FinFET. RTN of HTFET at VGS=0 V is higher for a trap location at source-channel tunnel junction. To analyze flicker, shot, and thermal noise, we created transistor level Verilog-A-based electrical noise models. The results indicate HTFETs competitive noise performance in megahertz frequency range, over Si-FinFET. In the range 10 GHz or more with operating voltages exceeding 0.3 V, HTFET input noise is worse due to the dominance of shot noise. A differential amplifier with active load is used to examine the electrical noise performance at circuit level. We emphasize that high intrinsic gain, drive current, and output resistance of HTFET can be used to achieve superior mixed signal performance metrics in HTFET design over Si-FinFET design, at an improved electrical noise performance.

Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications

As proliferation of embedded systems and mobile devices increases, power has become one of the most paramount concerns in current microprocessor designs. Technology scaling has provided many benefits in terms of dynamic power; however, static power has become the bottleneck to reducing power. We address this by evaluating Tunnel FETs (TFETs) for use in low-power, high-performance flip-flop designs. Due to the nature of TFETs, some of the flip-flop designs that are evaluated require additional modifications beyond simple device replacement-most notably the pseudo-static D flip-flop (DFF). We find that despite these additional transistors, the low voltage TFET DFF provides clear advantages in power and energy combined with performance comparable to higher voltage MOSFET and FinFET designs.

Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier

Hetero-junction Tunnel FET (HTFET) for ultra-low power RF circuit design has been explored at the device and circuit level. In this paper, benchmarking and design insights for optimizing the performance of the TFET based differential drive rectifier is presented. Our evaluation of the HTFET based rectifier demonstrates its promise compared to the state-of-art passive RFIDs. With the 10-stage optimized TFET rectifier at 915 MHz, PCE of 98% with 0.5 nW power consumption, sensitivity of -24dBm for 9 μW PDC and sensitivity of -33dBm for 0.4μW PDC were achieved.

Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications

A vertical device architecture having -40% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with Lg=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for VDD<;0.6V, while MOSFET is superior for VDD>;0.6V. To further improve MOSFET performance, ION needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (Cov and Cg,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.