Viktor Gruev

Implementation of steerable spatiotemporal image filters on the focal plane

This paper presents an architectural overview of a pseudogeneral image processor (GIP) chip for realizing steerable spatial and temporal filters at the focal-plane. The convolution of the image with programmable kernels is realized with area-efficient and real-time circuits. The chips architecture allows photoreceptor cells to be small and densely packed by performing all analog computations on the read-out, away from the array. The size, configuration, and coefficients of the kernels can be varied on the fly. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolution is implemented with a digitally programmable analog processor, resulting in very low-power consumption at high-computation rates. A 16/spl times/16 pixels prototype of the GIP has been fabricated in a standard 1.2-/spl mu/m CMOS process and its spatiotemporal capabilities have been successfully tested. The chip exhibits 1 GOPS/mW at 20 kft/s while computing four spatiotemporal convolutions in parallel.

Fabrication of a dual-tier thin film micropolarization array

A thin film polarization filter has been patterned and etched using reactive ion etching (RIE) in order to create 8 by 8 microns square periodic structures. The micropolarization filters retain the original extinction ratios of the unpatterned thin film. The measured extinction ratios on the micropolarization filters are approximately 1000 in the blue and green visible spectrum and approximately 100 in the red spectrum. Various gas combinations for RIE have been explored in order to determine the right concentration mix of CF(4) and O(2) that gives optimum etching rate, in terms of speed and under-etching. Theoretical explanation for the optimum etching rate has also been presented. In addition, anisotropic etching with 1 microm under cutting of a 10 microm thick film has been achieved. Experimental results for the patterned structures under polarized light are presented. The array of micropolarizers will be deposited on top of a custom made CMOS imaging sensor in order to compute the first three Stokes parameters in real time.

Linear Current-Mode Active Pixel Sensor

A current mode CMOS active pixel sensor (APS) providing linear light-to-current conversion with inherently low fixed pattern noise (FPN) is presented. The pixel features adjustable-gain current output using a pMOS readout transistor in the linear region of operation. This paper discusses the pixels design and operation, and presents an analysis of the pixels temporal noise and FPN. Results for zero and first-order pixel mismatch are presented. The pixel was implemented in a both a 3.3 V 0.35 and a 1.8V 0.18 CMOS process. The 0.35 process pixel had an uncorrected FPN of 1.4%/0.7% with/without column readout mismatch. The 0.18 process pixel had 0.4% FPN after delta-reset sampling (DRS). The pixel size in both processes was 10times10 mum2, with fill factors of 26% and 66%, respectively.

Linear current mode imager with low fix pattern noise

A new imaging architecture with a linear current mode active pixel sensor (APS) is presented. Focal plane image processing in the current domain includes a correlated double sampling (CDS) unit for fixed pattern noise (FPN) suppression. The CDS unit is composed of a first generation current conveyer circuit and a class AB cascaded current memory cell. A measured FPN of 0.9% from saturation level is achieved with the CDS unit compared to 1.9% FPN from current mode images without noise suppression circuitry. A 40 by 40 imaging array was fabricated in a standard 0.5 /spl mu/m process and its functionality was successfully tested. Theoretical analysis for second order non-linear effects is also presented.

A pipelined temporal difference imager

A 189/spl times/182 active pixel sensor (APS) for temporal difference computation is presented. The temporal difference imager (TDI), fabricated in 0.5-/spl mu/m CMOS process, contains in-pixel storage elements for a previous image frame. Difference double-sampling circuits are used to suppress the fixed pattern noise in both images and to compute the difference between the corrected images. The pixel area occupies 25 /spl mu/m by 25 /spl mu/m (using 0.7-/spl mu/m scalable rules), with fill factor of 30%. A novel pipelined readout technique is described, which is used to improve the accuracy of the temporal difference computation. With this pipelined readout architecture, >8-bit precision for the difference image and low spatial droop across the difference image is achieved. The chip consumes 30 mW at 50 fps from a 5-V power supply.

Current Mode Image Sensor With Two Transistors per Pixel

A linear current mode active pixel sensor for low fixed-pattern noise imaging is presented. The photo pixel is composed of a photodiode, a reset transistor, and a transconductance amplifier transistor. The address switch transistor is placed outside the pixel. The increased linearity of the pixel current coupled with current mode difference double sampling greatly reduces spatial variations across the image sensor array. The fabricated image sensor is composed of an array of 50 × 128 pixels and consumes 5 mW at 30 fps. Column fixed pattern noise of 0.1% from the saturated current and signal to noise ratio of 43.3 dB is achieved.

A CMOS linear voltage/current dual-mode imager

We present a CMOS image sensor capable of both voltage- and current-mode operations. Each pixel on the imager has a single transistor acting as either source follower for voltage readout, or transconductor for current readout. The two modes share the same readout lines, but have their own correlated double sampling (CDS) units for noise suppression. We also propose a novel current-mode readout technique using a velocity-saturated short-channel transistor, which achieves high linearity. The 300times200 image array is a mixture of 3 types of pixels with identical photodiodes and access switches; while the readout transistors are sized for their designated mode of operation. This ensures a fair comparison on the performance of the different modes

Image sensor with focal plane polarization sensitivity

A novel low power polarization image sensor is presented. This image sensor synergistically combines polymer polarization filters with a CMOS image sensor in order to compute the first three Stokes parameters at the focal plane. The carefully optimized microfabrication procedure for the pixel-pitch polymer polarization filters is described in detail in this paper. The imaging array is composed of 60 by 20 pixels and consumes 15 mW at 30 fps. A demo of the completed polarization image sensor will be given to illustrate how objects of similar luminescence can be discriminated based on their polarimetric properties.

Image sensor with focal plane extraction of polarimetric information

A novel focal plane imaging sensor capable of real time extraction of polarization information is presented. The imaging system consists of a photo array of 256 by 256 linear current mode active pixel sensors (APS). Analog processing circuitry is included at the focal plane for noise suppression and computation of the Stokes parameters. The imaging sensor was fabricated in 0.18mum process with 10mum pixel pitch and 75% fill factor. An array of micro polarizer is designed and fabricated separately and is mounted on top of the imaging array. Simulation results of the imaging sensor are presented

Neuromorphic Vision Systems for Mobile Applications

Neuromorphic vision systems are ideal for mobile applications because they promise compact computational sensing at lower power consumption compared to the traditional imager/ADC/CPU systems. These properties are particularly important for unmanned aerial vehicles. We present current-mode low noise imaging, which is typically difficult to realize, and computation-on-readout imaging processing for stereopsis and motion estimation. We discuss how these processed images can be used for guiding and controlling an autonomous aerial vehicle