Vincent J. Arkesteijn

Jitter requirements of the sampling clock in software radio receivers

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.

Cognitive radios for dynamic spectrum access - polyphase multipath radio circuits for dynamic spectrum access

Dynamic access of unused spectrum via a cognitive radio asks for flexible radio circuits that can work at an arbitrary radio frequency. This article reviews techniques to realize radios without resorting to frequency selective dedicated filters. In particular, a recently proposed polyphase multipath technique canceling harmonics and sidebands is discussed. Using this technique, a wideband and flexible power upconverter with a clean output spectrum has been realized on a CMOS chip, aiming at flexible radio transmitter application. Prototype chips can transmit at an arbitrary frequency between DC and 2.4 GHz. Unwanted harmonics and sidebands are more than 40 dB lower than the desired signal up to the 17th harmonic of the transmit frequency

A wideband high-linearity RF receiver front-end in CMOS

This paper presents a wideband high-linearity RF receiver-front-end, implemented in standard 0.18 /spl mu/m CMOS technology. The design employs a noise-canceling LNA in combination with two passive mixers, followed by lowpass-filtering and amplification at IF. The achieved bandwidth is >2 GHz, with a noise figure of 6.5 dB, +1 dBm IIP/sub 3/, +34.5 dBm IIP/sub 2/ and <50 kHz 1/f-noise corner frequency.