Vincenzo Peluso

Optimal parameters for /spl Delta//spl Sigma/ modulator topologies

A systematic study of single-loop, cascaded, and multibit /spl Delta//spl Sigma/ modulators of second to fourth order is presented, based on a combination of behavioral simulations and linear modeling. Constraints for optimal performance and precise guidelines for the choice of parameters are derived. Moreover, the optimal parameters and the corresponding performance are found and given in tables. A graph showing the maximal achievable performance of each topology as a function of the oversampling ratio is presented, offering a valuable help for the design of analog-to-digital converters.

A 15-b resolution 2-MHz Nyquist rate /spl Delta//spl Sigma/ ADC in a 1-/spl mu/m CMOS technology

A high-resolution high-speed fourth-order cascaded /spl Delta//spl Sigma/ analog-to-digital converter, based on a 2-1-1 topology, is presented. The converter is implemented with fully differential switched capacitor circuits in a standard 1-/spl mu/m CMOS technology. The converter uses two symmetrical reference voltages of 1 V, and is driven by a single 48-MHz clock signal. With an oversampling ratio of only 24, the converter achieves a resolution of 91 dB, a peak SNR of 90 dB, and a peak SNDR of 85 dB at a Nyquist rate of 2 MHz after comb filtering. The power consumption of the converter is 230 mW, from a single 5-V supply voltage.

Toward sub 1 V analog integrated circuits in submicron standard CMOS technologies

Lower channel lengths lead to lower supply voltages. For 0.25 /spl mu/m MOSTs the supply voltage is 2.5 V. Even lower supply voltages will follow. This paper deals with analog integrated circuits that can handle the reduction of the supply voltage down to 1 V. Existing solutions for such low supply voltages are: 1) reduction of threshold voltages from 0.7 V to 0.3-0.4 V; 2) use of voltage multipliers. It is possible to reduce supply voltages to 1 V in standard CMOS without voltage multipliers. The advent of deep submicron CMOS dictates reduced supply voltage.

Design of low-voltage low-power CMOS delta-sigma A/D converters

1. Introduction. 2. DeltaSigma Modulator Topologies. 3. The Switched Opamp Technique. 4. Low Voltage Circuit Design. 5. Design and Power Considerations. 6. Implementations. 7. Final Discussion. Appendices: A: Calculations for Chapter 3. B: Calculations for Chapter 4. C: Settling Analysis. References. Index.

A Dual-Channel Direct-Conversion CMOS Receiver for Mobile Multimedia Broadcasting

A 0.25mum CMOS receiver circuit that operates from 698MHz to 746MHz, a spectrum allocated by the FCC for advanced mobile services for multimedia applications, is presented. The receiver supports an OFDM physical layer with modulation ranging from BPSK for pilot carriers to 16-QAM for high-rate data carriers. The RX has a NF of 2.6dB and an out-of-band IIP3 of -5.5dBm. It occupies 7mm2 and draws 61mA from a 2.6V supply