Vinita Vasudevan

A numerical simulation of hole and electron trapping due to radiation in silicon dioxide

The one‐dimensional Poisson, continuity, and the trap rate equations are solved numerically to study the buildup of charge in silicon dioxide due to radiation. The flat‐band voltage shift (ΔVfb) is obtained as a function of total dose, the oxide thickness, the applied gate voltage, and the centroid of the trap distribution. The effect of including electron traps is studied. The results of the simulation are found to compare well with experimental data.

Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures

Reconfigurable hybrid processor systems provide a flexible platform for mapping data-parallel applications, while providing considerable speedup over software implementations. However, the overhead for reconfiguration presents a significant deterrent in mapping applications onto reconfigurable hardware. Partial runtime reconfiguration is one approach to reduce the reconfiguration overhead. In this paper, we present a methodology to map data-parallel tasks onto hardware that supports partial reconfiguration. The aim is to obtain the maximum possible speedup, for a given reconfiguration time, bus speed, and computation speed. The proposed approach involves using multiple, identical but independent processing units in the reconfigurable hardware. Under nonzero reconfiguration overhead, we show that there exists an upper limit on the number of processing units that can be employed beyond which further reduction in execution time is not possible. We obtain solutions for the minimum processing time, the corresponding load distribution, and schedule for data transfer. To demonstrate the applicability of the analysis, we present the following: 1) various plots showing the variation of processing time with different parameters; 2) hardware simulations for two examples, viz., 1-D discrete wavelet transform and finite impulse response filter, targeted to Xilinx field-programmable gate arrays (FPGAs); and 3) experimental results for a hardware prototype implemented on a FPGA board

A time-domain technique for computation of noise-spectral density in linear and nonlinear time-varying circuits

This paper presents a new time-domain technique for computing the noise-spectral density. The power-spectral density (PSD) is interpreted as the asymptotic value of the expected energy-spectral density per unit time. The methodology of stochastic differential equations is used to derive a set of ordinary differential equations for the expected energy-spectral density. This set of equations can then be integrated in time until the steady-state value of the PSD is obtained. The method can be used to find the noise spectrum in any circuit in which noise can be treated as a perturbation. The general nature of this algorithm has been illustrated in this paper by using it to get the noise-spectral density in switched-capacitor circuits, externally linear circuits and oscillators. The results match well with published experimental/analytical data.

A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters

In this paper, we propose a reconfigurable current-steering digital-to-analog converter (DAC). The differential nonlinearity error (DNL) of the DAC is estimated on-chip. This is used to reconfigure the switching sequence to get a lower integral nonlinearity error (INL). We propose a novel technique for estimation of DNL based on a step-size measurement. This greatly reduces the linearity and dynamic range requirements of the measuring circuits. A 10-b segmented DAC, along with the associated circuits for DNL estimation and reconfiguration, was designed using 0.35-/spl mu/m CMOS technology and fabricated through Europractice. The paper includes theoretical analysis, simulation, and experimental results for the proposed technique.

A simulation of the multiple trapping model for continuous time random walk transport

A multiple trapping model is used to study the dispersive transport of holes in insulators. The one‐dimensional Poisson and continuity equations are solved numerically along with the trap rate equations that model multiple trapping. The transient current due to a pulse of radiation is obtained as a function of the spread in the trap energy levels and the trap density distribution. The main properties of continuous time random walk transport, namely universality and superlinear dependence of the transit time on the electric field and oxide thickness, are verified.

A two-dimensional numerical simulation of oxide charge buildup in MOS transistors due to radiation

The authors have developed a time-dependent two-dimensional simulator in order to simulate charge trapping in silicon dioxide due to radiation. The Poisson and continuity equations are solved both in the oxide and the semiconductor. In addition, in order to simulate charge trapping, trap rate equations using first-order trapping kinetics are solved in the oxide. This paper contains the numerical methods used in the simulation and results obtained using this simulator. One of the main results of this simulation is the presence of a lateral variation in the radiation-induced oxide charge in an MOS transistor irradiated with a drain bias. >

A built-in-self-test scheme for digital to analog converters

This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in digital to analog converters (DACs). The BIST scheme measures each transition and estimates non-linearity errors. It makes use of a sample and subtract circuit and a VCO. The circuit is designed using 0.35 /spl mu/m CMOS technology from AMS. The simulation results are included in this paper. Errors estimated using the BIST scheme simulation match well with measured errors.

Hardware–software co-simulation of bus-based reconfigurable systems

Abstract One of the most flexible and modular approaches to reconfigurable systems is a bus-based approach. In order to get realistic performance estimates of these systems, detailed modeling of the processor as well as the bus and memory hierarchy is required. In addition, when coupling one or more reconfigurable units with a superscalar, out-of-order issue, load/store RISC CPU using the on-chip system bus, there are issues relating to cache coherency that need to be addressed. We have developed a cycle accurate co-simulator that uses a ‘C’ model of the processor and HDL models of the bus and reconfigurable units. We have also made modifications to the CPU pipeline to allow for non-cacheable accesses to the reconfigurable unit. This is reported in the paper. We have used this simulator to look at (a) The speedup obtained for two examples, namely, matrix multiplication and Lempel–Ziv compression, (b) the speedup obtained when there is a context switch from one application to the other and full reconfiguration is employed and (c) speedup obtained with partial reconfiguration. These results are reported in the paper.

Analysis of Clock Jitter in Continuous-Time Sigma–Delta Modulators

One of the factors limiting the performance of continuous-time sigma-delta modulators (CTSDMs) is clock jitter. This jitter can be classified as synchronous and accumulated/long-term jitter. A clock that is derived from a phase-lock loop contains both types of jitter. In this paper, we present a framework that can be used to obtain the output spectrum in the presence of jitter, either synchronous or accumulated or a combination of both. First, a general expression for the output power spectral density (PSD) of the CTSDM in the presence of clock jitter is derived. Based on this, analytical expressions for the output PSD are obtained for particular cases of synchronous and long-term jitter. These are validated against behavioral simulations.

A Skew-Normal Canonical Model for Statistical Static Timing Analysis

The use of quadratic gate delay models and arrival times results in improved accuracies for a parameterized block-based statistical static timing analysis (SSTA). However, the computational complexity is significantly higher. As an alternative to this, we propose a canonical model based on skew-normal random variables (SN model). This model is derived from the quadratic canonical models and can consider the skewness in the gate delay distribution as well as the nonlinearity of the MAX operation. Based on conditional expectations, we derive the analytical expressions for the moments of the MAX operator and the tightness probability that can be used along with the SN canonical models. The computational complexity for both timing and criticality analysis is comparable with SSTA using linear models. There is a two to three orders of magnitude improvement in the run time as compared with the quadratic models. Results on ISCAS benchmarks show that the SN models have a lower variance error than the quadratic model, but the error in the third moment is comparable with that of the semiquadratic model.