Vinod Pangracious

Three-Dimensional Integration: A More Than Moore Technology

Three-dimensional integrated circuits (3D-ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals and offer a promising solution for reducing both silicon footprint and interconnect length without shrinking the transistors. However, before these advantages can be realized, key technology and CAD challenges of 3D-ICs must be addressed. More specifically, the process required to build circuits with multiple layers of active devices and CAD tools used for design and validation of such circuits. Several such methodologies and CAD tools associated with the design fabrication of 3-D ICs are discussed in this chapter. Few successful 3D-IC design methods and CAD tools and benefits of applying 3D design to the future reconfigurable systems are also discussed in this chapter.

Artifical immune system using Genetic Algorithm and decision tree

Artificial immune system (AIS) is considered as an adaptive computational intelligence method that could be used for detecting and preventing current computer network threats. AIS generates Antibodies (self) competent in recognizing Antigen (non-self), which is considered as an anomaly technique. This paper aims to develop artificial immune system (AIS) that consists of two levels. Level one is developed using Genetic Algorithm, while level two is developed using C4.5 decision tree algorithm. The proposed system trained with clustered features that are selected from NSL-KDD cup data-set. Each level produces two antibodies (that could recognize Normal and Antigen access-records). The recognition accuracy of the developed system reaches 96%. The behavior of each level is studied. The best feature-set that suits each level is specified.

Physical Design and Implementation of 3D Tree-Based FPGAs

The semiconductor industries current enthusiasm for 3D-ICs is widespread and well warranted, but designing those 3D devices presents a challenge. Normal 2D design tools are thoroughly honed and refined over many years, nonetheless fail to address some of the critical issues of 3D-IC design. A new 3D-IC design process is evolving gradually from the 2D heritage. Today there are tools to handle a complete back-end flow and strides are being made to enable true 3D design and implementation using TSVs. In this chapter we discuss the design algorithms and techniques to develop 3D physical design tools and use of these tools to design and fabricate 3D stacked Tree-based FPGAs. This chapter starts with development of VHDL code generator and continue to the development 3D layouts of Tree-based FPGA using the 3D physical design tools developed for 3D FPGA design. A new CAD tool set for 3D physical design and verification based on Global Foundries 130 nm technology node modified to use Tezzaron’s TSV technology is also developed and presented in this chapter. Through this chapter we addressed few specific issues 3D designers often encounter dealing with tools that are not specifically designed to meet their needs. We also presented few additional 3D design support tools such as 3D LVS/DRC to verify the LVS of the partitioned and merged 3D designs.

A review of feature extraction for EEG epileptic seizure detection and classification

Epileptic seizure is one of the most common neurological diseases around the world. It is clinical symptoms and/or signs due to abnormal excessive or synchronous neuronal activity in the human brain. Electroencephalogram (EEG) that measures the electrical activity of the brain generated by the cerebral cortex nerve cells, is the most utilized test to detect the seizure activities by visual scanning of EEG signal recordings. Many techniques and methods have been proposed and developed to help the neurophysiologists to automatically detect the seizure activities with high accuracy. This paper presents a review of EEG features that have been proposed to characterize the epileptic seizure activities for the purpose of EEG seizure detection and classification. The relevant and discriminate features are analyzed, and their performance are also compared and discussed.

Novel Three-Dimensional Embedded FPGA Technology and Achitecture

In this paper we present a high density three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Trees (MoT) topology for an embedded FPGA architecture design targeted for high performance 3D integration. To obtain the optimal MoT-based interconnect structure, the routing architecture of the 2D MoT-based FPGA is modified to include long routing segments that span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, a 2.5D or 3D high density MoT-based embedded FPGAs can be designed. For the 3D multi-stacked MoT-based FPGAs, the 2D MoTbased FPGA is sliced into two or more equal sections by adjusting the length of the long wire span. The long wire segments are realized using 3D through silicon via (TSVs) and 2.5D interposer-based multi-FPGAs, we increase the number of cuts and apply appropriate optimization models to scale down the number of long wires and horizontal inter-FPGA interposer wires. Using our 2.5/3D CAD models, we demonstrate the speed and area of 3D MoT-based FPGA architecture improved by 54% and 41% respectively in comparison to 3D Mesh-based FPGAs.

Three-Dimensional FPGAs: Configuration and CAD Development

The primary focus of this chapter is to demonstrate a 3D integration scheme to partition and optimize the multilevel programmable interconnect network of Tree-based FPGA based on Butterfly-Fat-Tree network topology, where TSVs are incorporated in active layers of the 3D chip. This chapter describes the details of the architecture of 3D FPGAs and state-of-the-art 3D technology for Mesh-based FPGAs. To take advantage of 3D integrated circuits, it should be investigated how FPGA should be physically partitioned into different active layers. Proper physical partitioning has a great impact on the performance improvement of the system. This chapter discuss different partitioning schemes and design techniques and associated 3D CAD tools of 3D FPGAs.

An Overview of Three-Dimensional Integration and FPGAs

The capabilities of many digital electronic devices are strongly linked to Moore’s law: processing speed, memory and functional capacity and even the number and size of pixels in digital cameras. All of these are improving at roughly exponential rates as well. This exponential improvement has dramatically enhanced the impact of digital electronics in nearly every segment of the semiconductor industry, and is a driving force of technological and social change in the late 20th and early 21st centuries. This chapter discusses the historical evolution of semiconductor industry from 2D CMOS based technologies to today’s three-dimensional (3D) integrated circuits using 3D vertical interconnects. Our main focus in this book is to explain the need and the development of tools and technologies that supports the utilization this emerging technology to improve the performance and manufacturability of high density Field Programmable Gate Arrays (FPGAs).

Three-Dimensional Tree-Based FPGA: Architecture Exploration Tools and Technologies

Modern FPGAs have become a viable alternative to cell-based design technology by providing re-configurable computing platforms with improved performance and higher density using 3D integration technology. While the re-configurability provides flexibility, FPGAs also lead to area and performance overhead in comparison to cell-based custom integrated circuits (ICs). Thus to combine the advantages of both FPGAs and custom ICs, modern 3D heterogeneous FPGAs emerged as an attractive solution for system-on-chip implementations. The modern FPGAs include design components such as digital signal processors, on chip memory blocks, multipliers, adders, and entire processors. In this chapter our primary focus is on teaching the development of 3D FPGA tools and technologies and the validation of architecture exploration tools and optimization methodologies by using custom designed 3D homogeneous and heterogeneous Tree-based FPGAs.

Three-Dimensional FPGAs: Future Lines of Research

In this book, a collection of 3D FPGA architecture exploration, physical design, implementation methodologies and CAD tools for Tree-based FPGA architecture has been described and evaluated. We developed new and practical 3D Tree-based interconnect topologies and architecture to improve the performance, area and logic density for modern FPGA designs. While the research work presented in this book is an important step in the development of 3D FPGAs and CAD tools that can support the design and implementation of modern FPGA architectures, there is much work that remains. Here we give few new research directions to improve the 3D FPGA technology described in this book to cover the gap between FPGA and ASIC and to make FPGA technology competent enough to reduce the exorbitant cost of design and manufacturing.

Field Programmable Gate Arrays: An Overview

Field Programmable Gate Arrays (FPGAs) are semiconductor devices that contain logic components connected by a regular, hierarchical programmable interconnect system. The distinguishing characteristic of FPGAs is their on-filed programmability which allows the logic functionality of an FPGA to be re-programmed even after the manufacturing process. FPGAs are used for rapid prototyping of digital circuits. The design and test of digital systems are time efficient and cost-effective with FPGAs. The logic components in the FPGA mostly consists of memory elements such as registers or even complete blocks of memory that can be configured to hold any desired state. The hierarchical interconnect system is also programmable which allows the logic components to be connected in a variety of network configurations. Therefore the re-programmability of FPGAs is achieved by a fixed underlying architecture, which does not cater to any particular logic circuit. This lets FPGAs have a lower non-recurring cost, shorter design cycle and enables them to be re-programmed in the field to circumvent manufacturing defects. This chapter discuses about the FPGA building blocks and how they are interconnected to form a flexible digital prototyping and design platform.