Vinod Viswanath

Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems

This paper presents a novel technique for proving the correctness of arithmetic circuit designs described at the register transfer level (RTL). The technique begins with the automatic translation of circuits from a Verilog RTL description into a term rewriting system (TRS). We prove the correctness of the designs via an equivalence proof between TRSs for the implementation circuit design and a much simpler specification circuit design. We present this notion of equivalence between the TRSs and a stepwise refinement method for its decomposition, which we leverage in our tool Verifire. We demonstrate the effectiveness of our technique by using the tool for the verification of several multiplier designs that have hitherto been impossible to verify with existing approaches and tools.

Automatic decomposition for sequential equivalence checking of system level and RTL descriptions

Sequential equivalence checking between system level descriptions of designs and their register transfer level (RTL) implementations is a very challenging and important problem in the context of systems on a chip (SoCs). We propose a technique to alleviate the complexity of the equivalence checking problem, by efficiently decomposing it using compare points. Traditionally, equivalence checking techniques use nominal or functional mapping of latches as compare points. Since we operate at a level where design descriptions are in system level languages or hardware description languages, we leverage the information available to us at this level in deducing sequential compare points. Sequential compare points encapsulate the sequential behavior of designs and are obtained by statically analyzing the design descriptions. We decompose the design using sequential compare points and represent the design behavior at these compare points by symbolic expressions. We use a SAT solver to check the equivalence of the symbolic expressions. In order to demonstrate our technique, we present results on a non-trivial case study. We show an equivalence check between a SystemC description and two different Verilog RTL implementations of a Viterbi decoder, that is a component of the DRM SoC

Sequential equivalence checking between system level and RTL descriptions

Sequential equivalence checking between system level descriptions of designs and their Register Transfer Level (RTL) implementations is a very challenging and important problem in the context of Systems on a Chip (SoCs). We propose a technique to alleviate the complexity of the equivalence checking problem, by efficiently decomposing it using compare points. Traditionally, equivalence checking techniques use nominal or functional mapping of latches as compare points. Since we operate at a level where design descriptions are in System Level Languages or Hardware Description Languages, we leverage the information available to us at this level in deducing sequential compare points. Sequential compare points encapsulate the sequential behavior of designs and are obtained by statically analyzing the design descriptions. We decompose the design using sequential compare points and represent the design behavior at these compare points by symbolic expressions. We use a SAT solver to check the equivalence of the symbolic expressions. In order to demonstrate our technique, we present results on a non-trivial case study. We show an equivalence check between a System C description and two different Verilog RTL implementations of a Viterbi decoder, that is a component of the DRM SoC.

Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL

We present dedicated rewriting, a novel technique to automatically prove the correctness of low power transformations in hardware systems described at the Register Transfer Level (RTL). We guarantee the correctness of any low power transformation by providing a functional equivalence proof of the hardware design before and after the transformation. We characterize low power transformations as rules, within our system. Dedicated rewriting is a highly automated deductive verification technique specially honed for proving correctness of low power transformations. We provide a notion of equivalence and establish the equivalence proof within our dedicated rewriting system. We demonstrate our technique on a non-trivial case study. We show equivalence of a Verilog RTL implementation of a Viterbi decoder, a component of the DRM SoC, before and after the application of multiple low power transformations.

Efficient Microprocessor Verification using Antecedent Conditioned Slicing

The authors present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardware designs at the register transfer level (RTL). Antecedent conditioned slicing prunes the verification state space, using information from the antecedent of a given LTL property. In this work, the authors model instructions of a pipelined processor as LTL properties, such that the instruction opcode forms the antecedent. The antecedent conditioned slicing to decompose the problem space of pipelined processor verification on an instruction-wise basis was used. We pass the resulting smaller, tractable problems through a lower level verification engine. We thereby verify that every instruction behaves according to the specification and ensure that non-target registers are not modified by the instruction. The SMV model checker to verify all the instruction classes of a Verilog RTL implementation of the OR1200, an off-the-shelf pipelined processor was used

On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs

We present a novel and highly automated technique for dynamic system level power management of System-on-a-Chip (SoC) designs. We present a formal system to represent power constraints and power intent as rules. We also present a Term Rewriting Systems based rule rewriting engine as our dynamic power manager. We provide a notion of formal correctness of our rule engine execution and provide a robust algorithm to dynamically and automatically manage power consumption in large SoC designs. There are two fundamental building blocks at the core of our technique. First, we present a powerful formal system to capture power constraints and power intent as rules. This is a self-checking system and will automatically flag conflicting constraints or rules. Next, we present a rewriting strategy for managing power constraint rules using a formal deductive logic technique specially honed for dynamic power management of SoC designs. Together, this provides a common platform and representation to seamlessly cooperate between hardware and software constraints to achieve maximum platform power optimization dynamically during execution. We demonstrate our technique in multiple contexts on an SoC design of the state-of-the-art next generation Intel smartphone platform.

Dedicated rewriting: Automatic verification of low power transformations in Register Transfer Level

We present dedicated rewriting, a novel technique to automatically prove the correctness of low power transformations in hardware systems described at the Register Transfer Level (RTL). We guarantee the correctness of any low power transformation by providing a functional equivalence proof of the hardware design before and after the transformation. We characterize low power transformations as rules, within our system. Dedicated rewriting is a highly automated deductive verification technique specially honed for proving correctness of low power transformations. We provide a notion of equivalence and establish the equivalence proof within our dedicated rewriting system. We demonstrate our technique on a non-trivial case study. We show equivalence of a Verilog RTL implementation of a Viterbi decoder, a component of the DRM SoC, before and after the application of multiple low power transformations. We further demonstrate the application of our technique on a completely different kind of hardware circuit, viz. microprocessors. We show the correctness of instruction-driven slicing algorithm as applied to the OR1200 microprocessor.

Failures and verification solutions related to untimed paths in SOCs

A fundamental manifestation of the system-level nature of the modern SOC has been in the explosion of untimed paths on a chip. A single chip is no longer a textbook synchronous entity. Thanks to the use of complex design methodologies like asynchronous clock domains, interacting dynamic power domains, aggressive dynamic reset schemes, the wide-spread use of timing exceptions, GALS etc., large swaths of a chip interact asynchronously. Their analysis is outside the sweetspot of logic simulation + STA work-horse. Naturally, associated chip failures are being encountered in increased numbers and have acquired an insidious aura because they are detected late in the design process with adverse effects on budgets and business models. This urgent problem has driven rapid innovation in EDA, leading to a static verification framework comprising of a synthesis of semantic analysis and formal methods that enables sign-off level confidence for failure modes arising from such untimed paths. The success of this new class of EDA tools is evidenced, for example, by the fact that every single SOC today is signed-off using a dedicated clock-domain-crossing verification tool. This is a new paradigm in that these new EDA tools are targeted solutions for critical failure modes, representing a change from the incumbent practice of trying to make generic tools like simulators work for any type of design failure. Such a solution-oriented approach is a template to mitigate verification complexity arising from other failure modes.