Vishnu Balan

A 3-V, 10-100-MHz continuous-time seventh-order 0.05/spl deg/ equiripple linear phase filter

This continuous-time filter is for high-data-rate read channel ICs. Based on the conventional 7/sup th/-order, 0.05/spl deg/ equiripple, linear phase prototype the lowpass cut-off frequency (Fc) is programmable from 10-100 MHz, magnitude boost is programmable up to 13 dB, and the low frequency group delay can be tuned up to /spl plusmn/30% [1, 2]. Implemented in a 0.29 /spl mu/m BiCMOS technology, the filter has 0.5 mm/sup 2/ core area and dissipates 120 mW at 3 V at 100 MHz.

A low-voltage regulator circuit with self-bias to improve accuracy

There are a number of applications where a voltage follower with low output impedance, capable of driving capacitive load, is required. In many cases, the load also consists of a resistor in parallel with a large capacitor. The operational amplifier (opamp) design for such loads is quite challenging when a high closed-loop bandwidth is also required. In this paper, a novel technique is presented whereby the opamp is biased off the load itself, thereby increasing accuracy while at the same time remaining simple enough to be compensated easily.