Vishnu Khemka

A double RESURF LDMOS with drain profile engineering for improved ESD robustness

This letter reports a novel 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes. This device features a double RESURF technique in conjunction with a deep drain engineered profile that eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation. Maximum second breakdown current (I/sub t2/) of 16 mA//spl mu/m has been realized in a 100 ns transmission line pulse (TLP) measurement even with a higher holding voltage of 20 V. ESD protection level in excess of 5 kV with an equivalent human body model (HBM) has been shown to be feasible for this device without significant compromise in device size.

A 0.25/spl mu/m CMOS based 70V smart power technology with deep trench for high-voltage isolation

Presents a 0.25/spl mu/m CMOS based smart power platform on a P++ substrate with a deep trench high-voltage isolation as a low-cost alternative to SOI in realizing significant analog shrink, reduction of substrate parasitics and 70V high-side capability without affecting analog matching and process complexity.

Detection and optimization of temperature distribution across large-area power MOSFETs to improve energy capability

Temperature distribution inside a large-area reduced-surface field (RESURF) lateral double-diffused MOSFETs (LDMOSFETs) is studied with the help of experiments and theoretical modeling. Diode sensors are integrated inside a large area device to map the temperature as a function of distance. Temperature distribution is then optimized with the help of distribution of power across the device. Several layout techniques are presented and experimentally demonstrated for realizing this power distribution. It is shown that power applied to the device can be graded across the device by varying the saturation drain current in different parts of the device. Conventional devices with uniform power distribution achieved a critical failure temperature of 650 K at a drain to source voltage of about 40 V with a corresponding energy of 160 mJ/mm/sup 2/, whereas devices with graded power distribution achieved a critical failure temperature of about 560 K, even though the total energy capability of the device increases to 192 mJ/mm/sup 2/. It is also shown that the destruction point in the device shifts from the center of the device to the periphery. It is observed that as the power is graded across the device there is a counter balancing effect created by the increased impact ionization around the periphery of the device, which limits the energy capability improvement to be gained. Reducing the impact ionization rate by operating the device at V/sub ds/=30 V showed an increase in critical temperature for the graded distribution device to 610 K.

Experimental and theoretical analysis of energy capability of RESURF LDMOSFETs and its correlation with static electrical safe operating area (SOA)

Thermal and electrical destruction of 55 V single and double reduced surface field (RESURF) lateral double-diffused MOSFETs (LDMOSFETs) in smart power ICs are investigated by experiments, simulations, and theoretical modeling. Static safe operating area (SOA) and single pulse dynamic SOA (energy capability) have been studied and correlated. Single RESURF device failure and hence the energy capability is controlled by electrical phenomenon for drain to source voltage near breakdown voltages, whereas the energy capability of the double RESURF device is shown to be controlled by thermal phenomenon for voltage ranges up to about 5 V below the breakdown voltage. Measured energy capability data have been used to obtain critical temperatures for device failure, which decreases with an increase in drain to source voltage. We have empirically shown using experimental data that if the dynamic SOA of the device comes within about 2-5/spl times/ of the static SOA boundary, the device failure is strongly influenced by avalanche multiplication. An analytical model based on Greens function formulation is derived and proposed which can predict energy capability of LDMOSFETs for a wide range of device geometry. The calculated data show excellent matching with the measurements and are within /spl plusmn/10%. A new technique of distributing power within a device by applying less power at the center and more at the edges is proposed, which realizes significant improvement in energy capability by optimizing the temperature distribution within the device.

A fully planarized 4H-SiC trench MOS barrier Schottky (TMBS) rectifier

A fully planarized 4H-SiC trench MOS barrier Schottky (TMBS) rectifier has been designed, fabricated and characterized for the first time. The use of a TMBS structure helps improve the reverse leakage current by more than three orders of magnitude compared to that of a planar Schottky rectifier. We have achieved a low reverse leakage current density of 6/spl times/10/sup -6/ A/cm/sup 2/ and a low forward voltage drop of 1.75 V at 60 A/cm/sup 2/ for the TMBS rectifier. The static current-voltage (I-V) and switching characteristics of the TMBS rectifier have been measured at various temperatures. A barrier height of 1.0 eV and an ideality factor of 1.8 were extracted from the forward characteristics. The switching characteristics do not change with temperature indicating the essential absence of stored charge.

A floating RESURF (FRESURF) LD-MOSFET device concept

This letter reports a novel device concept, which is an extension of the conventional reduced surface field (RESURF) concept. A heavily doped n-type floating region is introduced into the conventional device structure which allows the breakdown capability of the device to be increased significantly while at the same time making it high-side capable. This floating RESURF (FRESURF) device concept allows the realization of significantly higher breakdown voltage in a thin epitaxy based power integrated circuit (IC) technology. A FRESURF lateral double-diffused power MOS transistor is designed, fabricated and reported for the first time with breakdown voltages as high as 90 V as opposed to 55 V obtained from conventional device sharing same process and drift region doping.

A novel technique to decouple electrical and thermal effects in SOA limitation of power LDMOSFET

This letter reports a novel technique to isolate thermal and electrical failure mechanisms in a power LDMOSFET device by deactivating the parasitic bipolar transistor while maintaining the MOS gate control. It is shown that the energy capability of the device remains constant as a function of the drain voltage in the event of a purely thermal failure, whereas the standard device shows a decrease in energy capability indicating electrothermal coupling. Nevertheless, the standard device energy capability is close to that obtained in the case of pure thermal failure, indicating that the thermal phenomenon dominates in determining the device failure and that electrical effects, though present, only minutely influence the device failure.

Drain profile engineering of RESURF LDMOS devices for ESD ruggedness

This paper reports a novel 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes. This device features a double RESURF technique in conjunction with a deep drain engineered profile which eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation. Maximum second breakdown current (I/sub t2/) of 16 mA//spl mu/m has been realized in a 100 ns transmission line pulse (TLP) measurement even with a higher holding voltage of 20 V. ESD protection level in excess of 5 kV with an equivalent human body model (HBM) has been shown to be feasible for medium sized devices without significant compromise in device performance.

Trade-off between high-side capability and substrate minority carrier injection in deep sub-micron smart power technologies

In this paper we present an evaluation of trade-off capability between high-side capability and minority carrier injection into substrate in smart power technologies. While high-side capability is easier to accomplish on lightly doped p-type substrates, the suppression of minority carrier injection is extremely poor. Techniques such as active protection, while useful in stand-alone configuration, show significant problems in actual circuits in a product. On the other hand use of a P++ substrate to improve substrate injection suppression poses significant challenges in achieving high-side voltage. We propose a new scheme of integrating deep trench based isolation with P++ substrate to realize an excellent trade-off between the two.

Correlation between static and dynamic SOA (energy capability) of RESURF LDMOS devices in smart power technologies

In this paper, we demonstrate the correlation between small area device static SOA and large area device pulsed SOA for single and double RESURF LDMOS configurations. We also elucidate the thermal and electrical limitations to the dynamic SOA of large area devices through measurements and transient electrothermal simulations and demonstrate a significant improvement in the large area dynamic SOA for a previously reported double RESURF technique which realizes an excellent R/sub dson/-BV/sub dss/ trade-off. An analytical model is described which is capable of predicting energy capability of these devices for different device size and geometry.