T. Roggenbauer

A 0.25/spl mu/m CMOS based 70V smart power technology with deep trench for high-voltage isolation

Presents a 0.25/spl mu/m CMOS based smart power platform on a P++ substrate with a deep trench high-voltage isolation as a low-cost alternative to SOI in realizing significant analog shrink, reduction of substrate parasitics and 70V high-side capability without affecting analog matching and process complexity.

Detection and optimization of temperature distribution across large-area power MOSFETs to improve energy capability

Temperature distribution inside a large-area reduced-surface field (RESURF) lateral double-diffused MOSFETs (LDMOSFETs) is studied with the help of experiments and theoretical modeling. Diode sensors are integrated inside a large area device to map the temperature as a function of distance. Temperature distribution is then optimized with the help of distribution of power across the device. Several layout techniques are presented and experimentally demonstrated for realizing this power distribution. It is shown that power applied to the device can be graded across the device by varying the saturation drain current in different parts of the device. Conventional devices with uniform power distribution achieved a critical failure temperature of 650 K at a drain to source voltage of about 40 V with a corresponding energy of 160 mJ/mm/sup 2/, whereas devices with graded power distribution achieved a critical failure temperature of about 560 K, even though the total energy capability of the device increases to 192 mJ/mm/sup 2/. It is also shown that the destruction point in the device shifts from the center of the device to the periphery. It is observed that as the power is graded across the device there is a counter balancing effect created by the increased impact ionization around the periphery of the device, which limits the energy capability improvement to be gained. Reducing the impact ionization rate by operating the device at V/sub ds/=30 V showed an increase in critical temperature for the graded distribution device to 610 K.

Experimental and theoretical analysis of energy capability of RESURF LDMOSFETs and its correlation with static electrical safe operating area (SOA)

Thermal and electrical destruction of 55 V single and double reduced surface field (RESURF) lateral double-diffused MOSFETs (LDMOSFETs) in smart power ICs are investigated by experiments, simulations, and theoretical modeling. Static safe operating area (SOA) and single pulse dynamic SOA (energy capability) have been studied and correlated. Single RESURF device failure and hence the energy capability is controlled by electrical phenomenon for drain to source voltage near breakdown voltages, whereas the energy capability of the double RESURF device is shown to be controlled by thermal phenomenon for voltage ranges up to about 5 V below the breakdown voltage. Measured energy capability data have been used to obtain critical temperatures for device failure, which decreases with an increase in drain to source voltage. We have empirically shown using experimental data that if the dynamic SOA of the device comes within about 2-5/spl times/ of the static SOA boundary, the device failure is strongly influenced by avalanche multiplication. An analytical model based on Greens function formulation is derived and proposed which can predict energy capability of LDMOSFETs for a wide range of device geometry. The calculated data show excellent matching with the measurements and are within /spl plusmn/10%. A new technique of distributing power within a device by applying less power at the center and more at the edges is proposed, which realizes significant improvement in energy capability by optimizing the temperature distribution within the device.

Trade-off between high-side capability and substrate minority carrier injection in deep sub-micron smart power technologies

In this paper we present an evaluation of trade-off capability between high-side capability and minority carrier injection into substrate in smart power technologies. While high-side capability is easier to accomplish on lightly doped p-type substrates, the suppression of minority carrier injection is extremely poor. Techniques such as active protection, while useful in stand-alone configuration, show significant problems in actual circuits in a product. On the other hand use of a P++ substrate to improve substrate injection suppression poses significant challenges in achieving high-side voltage. We propose a new scheme of integrating deep trench based isolation with P++ substrate to realize an excellent trade-off between the two.

A 0.35 /spl mu/m CMOS based smart power technology for 7 V-50 V applications

This paper describes a 0.35 /spl mu/m smart power technology that enables integration of a diverse set of analog and high-voltage power components in a 0.35 /spl mu/m CMOS logic platform for a broad range of voltage applications from 7 V to 50 V.

A 65 V, 0.56 m/spl Omega/.cm/sup 2/ Resurf LDMOS in a 0.35 /spl mu/m CMOS process

This paper reports a 65 V, 0.56 m/spl Omega/.cm/sup 2/ Resurf LDMOS with a wide safe operating area integrated into a 0.35 /spl mu/m CMOS process. The superior performance of the device is achieved by advanced implantation techniques without additional thermal steps and without resorting to high-tilt implants.

A nondestructive electrical test structure to monitor deep trench depth for automated parametric process control

A novel nondestructive measurement technique is proposed to electrically monitor the depth of a trench etched in silicon for the purpose of process control in a manufacturing environment. A simple bipolar npn transistor can be constructed, the gain of which is shown to relate to the trench depth. The ratio of the injected emitter current to the captured collector current has demonstrated the ability to resolve variations in trench depth of less than 0.2 /spl mu/m. The proposed structure is studied using two-dimensional simulations and experiments. A case study of two different silicon reactive ion etch tools is offered to demonstrate the effectiveness of the proposed technique.

An electrical monitor of deep trench depth

A novel, non-destructive measurement technique has been used to electrically monitor the depth of a deep trench in a submicron smart power process. The ratio of the injected emitter current to the captured collector current in a parasitic bipolar transistor has demonstrated the ability to resolve variations in trench depth of <0.2 /spl mu/m and was used to qualify a new etch process.