Vishnu P. Nambiar

Hardware Acceleration of OpenSSL Cryptographic Functions for High-Performance Internet Security

The Transport Layer Security (TLS) protocol is currently the predominant method of implementing Internet security. This paper proposes an FPGA-based embedded system integrating hardware that accelerates the cryptographic algorithms used in the SSL/TLS protocol. OpenSSL, an open source implementation of the SLL v3 and TLS v1 protocol, is deployed in the proposed embedded system powered with a Nios-2 embedded soft-core processor. Nios2-Linux RTOS is applied, which serves to provide Ethernet connectivity, multitasking, and support for the OpenSSL library. Key cipher functions used in SSL-driven connections, which include AES-256 symmetric encryption, SHA-2 hashing, RSA-2048 publickey cryptography, are accelerated in hardware. The embedded cryptosystem is prototyped completely on an Altera Stratix II FPGA development board. Experimental results show significant improvements in performance of the SSL transactions when the proposed embedded cryptosystem is deployed in the networking system.

Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function

This paper presents the hardware implementation of an evolvable block-based neural network that utilizes a novel and cost efficient sigmoid-like activation function. Evolvable block-based neural networks (BbNNs) feature simultaneous optimization of structure, and viable implementation in reconfigurable digital hardware such as field programmable gate arrays (FPGAs). Efficient hardware implementation of BbNN structures is the primary goal of this paper. Various aspects of BbNN modeling and design considerations are presented. The neuron blocks are designed with properly described methodology, using only a single multiplier each, and implement a cost efficient sigmoid-like activation function. A novel method of reusing the multiplier to smoothly approximate a hyperbolic tangent (tanh) function to be used as the activation function for the neuron blocks is also presented. This is an important contribution, because a sigmoid-like activation function is provided at almost no additional cost. The neuron blocks are very cost efficient in terms of logic utilization when compared to the previous work. The BbNN is designed as an system-on-chip (SoC), and is functionally verified and tested on several case studies. The system performance allows real-time classification, and executes up to 410×faster than embedded software.

HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems

This paper describes the implementation of a reconfigurable hardware-based genetic algorithm (HGA) accelerator using the hardware-software (HW/SW) co-design methodology. This HGA is coupled with a unique TRNG that extracts random jitters from a phase lock loop (PLL) to ensure proper GA operation. It is then applied and benchmarked with several case studies, which include the optimization of a simple fitness function, a constrained Michalewicz function, and the tuning of parameters in finger-vein biometrics. A HGA solution is necessary in systems that demand high performance during the optimization process. However, implementations that are completely designed in hardware will result in a very rigid architecture, making it difficult to reconfigure the system for use in different applications. This paper aims to solve this issue by proposing a HGA design that provides reconfigurability and flexibility by moving problem-dependent processes into software. The prototyping platform used is an Altera Stratix II EP2S60 FPGA prototyping board with a clock frequency of 50 MHz. The HW/SW co-design technique is applied, and system partitioning is done based on aspects such as system constraints, operational intensity, process sequencing, hardware logic utilization, and reconfigurability. Experimental results show that the proposed HGA outperforms equivalent software implementations compiled with an open-sourced C++ GA component library (GAlib) running on the same prototyping platform by 102 times at most. In the final case study, the application of the proposed HGA in tunable parameter optimization in finger-vein biometrics improved the matching rate, reducing the equal error rate (EER) value from 1.004% down to 0.101%.

An AES Tightly Coupled Hardware Accelerator in an FPGA-based Embedded Processor Core

This paper presents the implementation of a tightly coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate Advanced Encryption Standard (AES) operations in 128, 192 and 256-bits, for application in a high-performance embedded system implementing symmetric key cryptography. The concept is to augment the embedded processor with a new custom instruction for encryption and decryption operations. In order to show the effectiveness of tightly coupled hardware implementation over coprocessor based approach, we have also realized the design in coprocessor approach using the same AES core. Experimental results show that for the encryption or decryption operations, real implementation with custom instructions and tightly coupled hardware is about 35% faster than the co-processor based hardware.

Evolvable Block-based Neural Networks for real-time classification of heart arrhythmia From ECG signals

Heart arrhythmia is a fairly common medical condition, in which abnormal electrical activity occurs in the heart. However, it can be life threatening if left untreated or undiagnosed. This paper introduces an improved method to classify heart arrhythmia from electrocardiogram (ECG) signals using Block-based Neural Networks (BbNN). BbNNs are used in the hardware implementation of this problem due to its regular block based structure, relatively fast computational speeds, and lower resource consumption. The training mechanism for evolving BbNNs used in the work utilizes Genetic Algorithm (GA), but is able to handle larger sets of training data more efficiently due to an implementation of a novel multithreaded fitness evaluation approach. The ECG heartbeat dataset is taken from the MIT-BIH arrhythmia database, and feature extraction is done using the evaluation of Hermite polynomials on the preprocessed ECG signal. The proposed BbNN system-on-chip (SoC) shows high accuracy in its arrhythmia classification, with an average accuracy of 99.64% for all tested patient records.

Accelerating the AES encryption function in OpenSSL for embedded systems

The Internet is an insecure medium. In embedded systems however, network security comes at a very high cost. While there are freely available solutions such as the OpenSSL library, the performance of most embedded processors, on their own, are just not adequate enough to perform cryptography for realtime applications. In this paper, we focus on the implementation of a cryptographic embedded system deploying an Altera Nios II embedded processor working with an AES encryption hardware accelerator. The RTOS applied is uClinux, on which the OpenSSL library has been ported and cross compiled. Experimental results show that hardware acceleration can improve the performance of OpenSSL cryptographic functions, and hence, of the SSL connection as well.

GA-based parameter tuning in finger-vein biometric embedded systems for information security

As concerns about security in networking and communication systems rise with their rapid technology advancements, the need for more reliable and stronger user authentication techniques has also increased. Traditional security methods such as personal identification number, password, and key smart cards are proving to be more and more inadequate, especially in large-scale authentication systems. Hence today, the biometric-based security system is gaining acceptance as an effective tool for providing information security, as can be seen by its deployment in various commercial, public, border control and governmental applications. Each biometric technique has its own merits, but recently, finger-vein biometrics has shown great promise with some key advantages over the other biometrics, which include fingerprint, face, iris and voice. Research has shown that finger-vein biometrics yield very low error equal rates (EER). However, there is more room for improvement. This paper presents a method to optimize finger-vein detection by using genetic algorithms (GA) to fine-tune the image processing parameters in an finger-vein biometric FPGA-based system-on-chip embedded system. The parameters that are tunable include threshold levels and filtering parameters. Experimental results show that the optimization process can successfully reduce the EER from 1.004% to 0.101% on the same biometric system, negating the need for an expert system designer intuition on the image processing parameters.

Co-simulation methodology for improved design and verification of hardware neural networks

This paper presents a methodology for speeding up the design and verification of process of artificial neural networks (ANNs) in system-on-chip (SoC) hardware with the help of co-simulation. Application of advanced design methodologies for complex designs such as ANNs are important in todays fast moving hardware design industry. However, it is difficult to fully verify the functionality of ANNs when designed in hardware. Most forms of ANN require the use of complex training algorithms, which are difficult to implement in a testbench even with the help of modern interfaces such as SystemVerilogs DPI-C. The neural network topology selected as the case study for this paper are evolvable block-based neural networks (BbNNs). The case studies employed during the verification process are the XOR problem, driver drowsiness classification, and heart arrhythmia classification. The proposed methodology significantly reduces the verification time required for the design of hardware-based neural networks. This allows complex models applicable a variety of applications to be quickly designed, such as industrial motor controllers or fuzzy systems.