Vladimir Trujillo-Olaya

Hardware implementation of the Smith-Waterman algorithm using a systolic architecture

This paper presents the design of a systolic processor for DNA local pairwise alignment. The main building block of the processor is a 1D array of processing elements that allows pipeline processing to reduce the execution time with respect to software tools. We aligned two sequences of 4096 nucleotides from the ABO blood group gene of human and house mouse using ModelSim-Altera to verify the hardware design. The hardware simulation results were compared with software simulation results, showing the functionality of the design. The design can only be synthesized on the targeted FPGA for processing 256 nucleotides simultaneously due to hardware limitations (ALUTs and registers), but could be implemented for aligning larger sequences by using a bigger device or FPGA arrays. The design could also be used to implement other dynamic programming algorithms by modifying the processing element.

Design of an 8192-bit RSA cryptoprocessor based on systolic architecture

This paper presents the design of an 8192-bit RSA cryptoprocessor using a radix 2 Montgomery multiplier based on a systolic architecture. In this case, the Montgomery multiplier simultaneously performs two multiplications, and the cryptoprocessor carries out the modular exponentiation using the binary exponentiation algorithm. The designs are described using generic structural VHDL and synthesized on the EP3SL150F1152C2, using Quartus II 11. The hardware synthesis and performance results show that the designed cryptoprocessor presents a good area-throughput trade-off and it can be used as a suitable core for an RSA cryptosystem embedded into a SoC.

Analysis of performance versus security in hardware realizations of small elliptic curves for lightweight applications

Abstract In this paper, we report the results of a comprehensive study of the security level versus the execution performance (and resource requirements) for hardware implementations of small elliptic curves, particularly targeted for lightweight applications, such as RFID tags and sensor nodes. The case study was performed for small elliptic curves (41–163 bits) over GF(

Hardware architectures for inversion in GF(2 m ) using polynomial and gaussian normal basis

2^m

Efficient Hardware Implementations for the Gaussian Normal Basis Multiplication Over GF(2163)

), where finite field elements are represented using polynomial and Gaussian normal bases. The idea behind using elliptic curves in this range is that we obtain small implementations suitable for the mentioned applications, however, this would be at the cost of less security since the Elliptic Curve Discrete Logarithm Problem (ECDLP) would be easier to break, i.e., would require fewer resources and less time for such small curves. Therefore, one must investigate both sides of the coin: first, hardware resources to implement such elliptic curves and the resulting total execution time for a single point multiplication; second, hardware resources to break such a curve and the resulting cost in terms of a defined metric, such as the total amount devices or dollars to solve the ECDLP in a given time duration. Following this reasoning, we studied the hardware (FPGA) implementations of small elliptic curves and determined the amount of resources (number of ALUTs, MEMs, REGs, the duration of clock, the total number of clock cycles and the total execution time) needed for a single point multiplication operation. We also studied the security level of each one of these curves, based on an attack model an associated cost metric. Under our proposed attack model, which we believe is very innovative; we considered three different platforms, namely PC, FPGA, and cloud computing. Due to the complexity of Cloud Computing configurations, we considered two different performance instances, namely, small (low budget) and high performance (relatively high budget). We then calculated the amount of resources and the total amount of dollars needed to solve each particular ECDLP, under different assumptions. We believe the results of our study will allow designers to select the appropriate curve for each application and the device, based on the perceived (or real) threat models that device is operating and the performance requirements of the elliptic curve protocol, such as ECDH, ECDH, or ECIES.

Design of elliptic curve cryptoprocessors over GF(2 163 ) on Koblitz curves

This paper presents the design of an elliptic curve cryptoprocessor using optimal normal basis. The scalar point multiplication is implemented using random curves over GF(2233), and the finite field multiplication is implemented using bit-serial and parallel multiplication algorithms. The designed processor is flexible, parameterized and described by using VHDL. This allows achieving a good trade-off between area, performance and flexibility. The execution times to carry out the scalar point multiplication of the designed cryptoprocessor using bit-serial and parallel multiplication were 1.62 μs and 0.025 μs, respectively. The performance results show that this cryptoprocessor can be used as a hardware coprocessor for high performance reconfigurable cryptosystems.

8912-bit Montgomery multipliers using radix-8 booth encoding and coded-digit

This paper presents the hardware architectures for inversion in GF(2m), in order to be used in elliptic curve cryptosystems. In this case, the Extended Euclidean Algorithm (EEA) and the Itoh-Tsujii Algorithm (ITA) are implemented. The simulation were carried out using Quartus II v. 9,0 and the design were synthesized on the Stratix III EP3SE50F780C2. The simulation results show a very good performance using small area.

Bit-flip injection strategies for FSMs modeled in VHDL behavioral level

This work presents the hardware implementation of four hardware profile stream ciphers from the eSTREAM project. The hardware architectures are implemented using structural VHDL and, taking into account the simulation results, the best algorithm for hardware implementation is Trivium, with an 80-bit security level. This implementation requires 8 ALUTs, 289 registers, has a maximum frequency of 915.75 MHz and a throughput of 915 Mbps. The second is Grain-128, followed by Mickey-128 and Decim-128, which have a 128-bit security level. The designs were synthesized on the Altera FPGA Stratix ΙΠ EP3SE50F484C2.