Vladimir Ya. Stenin

Design of logical elements for the 65-nm CMOS translation lookaside buffer with compensation of single events effects

Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix in arrays of Content-Addressable Memory (CAM) cells and RAM cells. The basis of the coincidence logic of CAM is combinational logic elements with the single-event compensation using masking and compensation.

Design of logical elements with single-event compensation for the 28-nm CMOS decoders

Logical elements with Single-Event Transients Compensation were simulated on the base of the bulk 28-nm CMOS design rule. The result of an impact of a single nuclear particle on MOS logical gate is a noise pulse, being a single-event transient. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output state null “0” of bits error decoder by masking and compensation.

Single event transients in 28-nm CMOS decoders

RAM decoders were simulated on base the bulk CMOS 28-nm design rule. The result of a single nuclear particle impact on a MOS logical gate is a noise pulse as a single-event transient. The internal error decoder gives the main contribution to a noise sensibility of a RAM decoder. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output state 0 of bits error decoder by masking and quenching.

The multiport CMOS memory cell based on the DICE trigger with two spaced transistor groups for hardened 65-nm CMOS SRAM

Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event transient, but not a single-event upset. The use of the new two groups DICE trigger with the spacing between the two groups more than 3 μm increases the soft-error immunity of the 65-nm multiport CMOS memory. In the address decoders, in registers of data and control of a multiport SRAM to improve immunity to the effects of single nuclear particles were used DICE flip-flops and combinational logic based on two-phase logic elements mutually spaced pairs of sensitive transistors on a chip. With these elements it was provided the minimum increase in the area as hardened multiport 65-nm CMOS memory cells, and the multiport SRAM while using guard rings and ohmic contacts compared with multiport cells and RAM on normal CMOS D-triggers.

The static RAM on DICE cells spaced onto two groups

Static RAM with a traditional topology of DICE designed by scaling with rules less than 65-nm lost advantages in failure tolerance to single nuclear particles compared to CMOS RAM on 6-T memory cells. Transistors of the STG DICE cell have been separated onto two groups so that impact of single nuclear particles on one of the groups do not lead to an upset of the logic state of the cell, but only causes a transient effect. Spacing and interleaving of several groups enables the maximum distances between the mutually sensitive nodes of the two groups of transistors of STG DICE. In this case, the area of the layer of active devices may be equal to the area of the layer of metallization in the basic memory elements. It allowed increasing the distance between mutually sensitive nodes of each of DICE cells to values more than 2 μm. This approach ensured the increase of additional area of the DICE cell 15 % only. Static cache RAMs as parts of the microprocessor system in bulk CMOS 65 nm technology were tested for the upset immunity using the laser pulse technique.