Vojin G. Oklobdzija

Energy-Efficient Design Methodologies: High-Performance VLSI Adders

Energy-efficient design requires exploration of available algorithms, recurrence structures, energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In this paper, methodology for energy-efficient design applied to 64-bit adders implemented with static CMOS, dynamic CMOS and CMOS compound domino logic families, is presented. We also examined 65 nm, 45 nm, 32 nm, and 22 nm technology nodes to explore the applicability of the results in deep submicron technologies. By applying energy-delay tradeoffs on various levels, we developed adder topology yielding up to 20% performance improvement and 4.5× energy reduction over existing designs.

Energy efficient implementation of parallel CMOS multipliers with improved compressors

Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16×16-bit Booth and Non-Booth multipliers are analyzed in energy and delay space under varying constraints. It is shown that Non-Booth multipliers start to become more energy efficient for strict delay targets. In addition, novel 3:2 and 4:2 compressors are presented to save energy at the same target delay. The proposed compressors provide up to 20% energy reduction depending on the target delay at 65nm CMOS technology. Non-Booth multiplier implemented with the proposed compressors provides performance advantage as the voltage is scaled from its nominal value. Further, we examined all designs in 45nm, 32nm and 22nm CMOS technology nodes.

Soft error filtered and hardened latch

this paper presents a low-power soft error-hardened latch suitable for reliable circuits. The proposed circuit uses redundant feedback loop to protect latch circuit against soft error on the internal nodes and skewed CMOS to filter out transients resulting from particle hit on combinational logic. The proposed circuit has low power consumption, enhanced setup time and lower timing overhead. The HSPICE post-layout simulations in 90nm CMOS technology reveals that circuit is able to recover from single particle strike on internal nodes and tolerates input SETs up to 130ps of duration.

Exploration of switching activity behavior of addition algorithms

Total energy consumption of a micro-architecture directly depends on the switching factors of the internal nodes. Weinberger and Ling are the most widely used binary addition algorithms that are used in microprocessor adders. In this paper, the switching activity behaviors of those well known addition recurrence structures are explored. The formulae for estimation of switching activity rates of signals given the probabilities of input signals are derived. The results reveal that the preference of one addition algorithm to other one in terms of switching factors depends on the statistical properties of the input signals as well. The addition algorithms are examined on Kogge-Stone structure and it is possible to save energy up to 20% by selection of the proper addition algorithm in 64-bit adders.

Switching activity calculation of VLSI adders

Using exact switching activity rates at all internal nodes when calculating energy of digital circuits is believed to result in improved accuracy over to the use of average switching activity.We compare the two approaches in the case of the Kogge-Stone adder implemented with Weinberger and Ling addition recurrences. The difference between the two is less than 4%.Further we examined the accuracy of the energy/delay estimation technique when using exact and average switching activities in 65nm, 45nm, 32nm and 22nm technology nodes. Even then the worse case error in estimating energy is under 15% at 22nm technology node for 64-bit Kogge-Stone adder. The error in delay estimation is less than 6% for all the nodes. Our finding is that using average switching activity does not yield large errors while simplifying the estimation process greatly.

Low-power soft error hardened latch

This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft error on the internal nodes, and transmission gate and Schmitt-trigger circuit to filter out transient resulting from particle hit on combinational logic. The proposed circuit has low power consumption with negative setup time and low timing overhead. The HSPICE post-layout simulation in 90nm CMOS technology reveals that circuit is able to recover from almost any single particle strike on internal nodes and tolerates input SETs up to 130ps of duration.

Clocked storage elements robust to process variations

In this work, different types of clocked storage elements are compared in terms of the impact of process variations on their performances. Transistor sizes are obtained from energy-efficient characteristics and used in the simulation to measure the delay variations caused by process variations. The structure of a clocked storage element affects its robustness to process variations.

Design Methodology for Clocked Storage Elements Robust to Process Variations

In this paper we address the effects of process variations on the performance of clocked storage elements. Two types of structures are selected and evaluated by using energy-delay space analysis. The delay variations of the energy-efficient designs for each clocked storage element are measured and compared. We show how much topology selection is important in order to minimize the impact of process variations on performance and reliability.

Design of a link-controller architecture for multiple serial link protocols

This paper introduces a novel Multi-mode Serial Link Controller (MMSLC) for logic physical layer (PHY) and data link layer (DLL) of USB 3.0, PCIe 2.0 and SATA 3.0. Functions defined in these protocols are grouped based on qualifying similarities and workload. The framework consists of a configurable circuit, programmable accelerator and event processor for flexible implementation. This MMSLC can essentially substitute for three individual link-controllers across protocols, thus achieving area reduction. An RTL level implementation is fulfilled and the synthesis results are shown at the end of this paper.

Computing at the ultimate low-energy limits

Given the fixed performance target, various parameters such as transistor sizing, supply voltage, transistor threshold and bias are the parameters determining the amount of energy required. While these parameters can be independently tuned, there is a physical limit determining the minimal amount of energy needed in order to achieve target performance. This lecture will examine various optimization parameters and inter-relationship between various transistor and circuit design parameters leading to computation with minimal energy.