Vwani P. Roychowdhury

Segmented channel routing

Routing channels in a field-programmable gate array contain predefined wiring segments of various lengths. These may be connected to the pins of the gates or joined end-to-end to form longer segments by programmable switches. The segmented channel routing problem is formulated, and polynomial time algorithms are given for certain special cases. The general problem is NP-complete, but it can be adequately solved in practice. Experiments indicate that a segmented channel with judiciously chosen segment lengths may near the efficiency of a conventional channel.

Efficient algorithms for reconfiguration in VLSI/WSI arrays

The issue of developing efficient algorithms for reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources is discussed. The models discussed consist of a set of identical processors embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. An array grid model based on single-track switches is considered. An efficient polynomial time algorithm is proposed for determining feasible reconfigurations for an array with a given distribution of faulty processors. In the process, it is shown that the set of conditions in the reconfigurability theorem is not necessary. A polynomial time algorithm is developed for finding feasible reconfigurations in an augmented single-track model and in array grid models with multiple-track switches. >

Stochastic modeling of citation slips

SummaryThis paper studied the intellectual structure of urban studies through a co-citation analysis of its thirty-eight representative journals from 1992 to 2002. Relevant journal co-citation data were retrieved from Social SciSearch, and were subjected to cluster analysis, multidimensional scaling, and factor analysis. A cluster-enhanced two-dimensional map was created, showing a noticeable subject variation along the horizontal axis depicting four clusters of journals differentiated into mainstream urban studies, regional science and urban economics, transportation, and real estate finance. The cluster of the mainstream urban studies journals revealed a higher degree of interdisciplinarity than other clusters. The four-factor solution, though not a perfect match for the cluster solution, demonstrated the interrelationships among the overlapping journals loaded high on different factors. The results also showed a strong negative correlation between the coordinates of the horizontal axis and the mean journal correlation coefficients reflecting the subject variation, and a less revealing positive correlation between the coordinates of the vertical axis and the mean journal correlation coefficients.

Scheduling in and out forests in the presence of communication delays

The authors consider the problem of scheduling tasks on multiprocessor architectures in the presence of communication delays. Given a set of dependent tasks, the scheduling problem is to allocate the tasks to processors such that the pre-specified precedence constraints among the tasks are obeyed and certain cost-measures (such as computation time) are minimized. Several cases of the scheduling problem have been proven to be NP-complete. Nevertheless, there are polynomial time algorithms for several interesting special cases of the general scheduling problem. Most of these results, however, do not take into consideration the delays due to message passing among processors. The authors study the increase in time complexity of the scheduling problem due to the introduction of communication delays. In particular, they address the open problem of scheduling out-forests (in-forests) in a multiprocessor system of m identical processors when communication delays are considered. They present first known polynomial time algorithms for the computation of the optimal schedule when the number of available processors is given and bounded and both computation and communication delays are assumed to take one unit of time.<<ETX>>

A geometric approach to threshold circuit complexity

We introduce a geometric approach for investigating the power of threshold circuits. Viewing n- variable boolean functions as vectors in R 2 n , we invoke tools from linear algebra and linear programming to derive new results on the realizability of boolean functions using threshold gates.

Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms

The study of Regular Iterative Algorithms (RIAs) was introduced in a seminal paper by Karp, Miller, and Winograd in 1967. In more recent years, the study of systolic architectures has led to a renewed interest in this class of algorithms, and the class of algorithms implementable on systolic arrays (as commonly understood) has been identified as a precise subclass of RIAs. In this paper, we shall study the dependence structure of RIAs that are not systolic; examples of such RIAs include matrix pivoting algorithms and certain forms of numerically stable two-dimensional filtering algorithms. It has been shown that the so-called hyperplanar scheduling for systolic algorithms can no longer be used to schedule and implement non-systolic RIAs. Based on the analysis of a so-called computability tree we generalize the concept of hyperplanar scheduling and determine linear subspaces in the index space of a given RIA such that all variables lying on the same subspace can be scheduled at the same time. This subspace scheduling technique is shown to be asymptotically optimal, and formal procedures are developed for designing processor arrays that will be compatible with our scheduling schemes. Explicit formulas for the schedule of a given variable are determined whenever possible; subspace scheduling is also applied to obtain lower dimensional processor arrays for systolic algorithms.

How to play bowling in parallel on the grid

Abstract Suppose that there are m players each situated at a node of a two-dimensional grid. Every player would like to play bowling by rolling the ball towards one of the boundaries of the grid. Clearly, the paths used by the players should be perpendicular to the boundaries and nonintersecting. We would like to maximize the number of players that are able to play, namely, to find an assignment, of maximum cardinality, of paths to players. Hence, we are interested in solving the following geometrical problem: given a set of m distinguished nodes in a two-dimensional grid, determine a set of non-intersecting straight lines of maximum cardinality such that every line starts at one of the distinguished nodes and connects it to one of the boundaries of the grid. Our main result is an O ( m 3 ) algorithm for solving the problem which is the first known polynomial time algorithm for this problem.

Study of parallelism in regular iterative algorithms

The study of Regular Iterative Algorithms (RIAs), which was introduced in a seminal pa.per by Knrp, Miller, and Winograd in 1967, forms the basis for systematic design and analysis of regular processor arrays, including the class of systolic arrays. The RIAs have also been studied under different contexts and different names (on the last count RIAs were reintroduced, as late as 1987, under the name of dynamic graphs). In spite of the interest such algorithms have received over the years, many important issues that were left unresolved in the original paper by Karp e2 al., have remained unanswered. In this paper we answer many such questions, particularly those relating to parallel scheduling and implementation of RIAs. Based on the analysis of a simple graph that captures the dependence structure of a given RIA, we are able to determine linear subspaces in the index space of a given RIA such that all variables lying on the same subspace can be scheduled at the same time; this generalizes the so-called hyperplanar scheduling which was shown by Karp et. al. to work for only a subclass of RIAs. This geometric scheduling scheme is shown to be asymptotically optimal and is used to completely characterize the extent of parallelism in any RIA. Moreover, we develop procedures to determine explicit schedules (;.e, a closed form expression for the schedule of every computation in the algorithm) that correspond to the geometric schedules, and also show that every RIA can be automatically mapped onto regular processor arrays. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific permission.

Some new algorithms for reconfiguring VLSI/WSI arrays

In this paper we present new algorithms for reconfiguring arrays of identical Processing Elements (PEs) in the presence of faults. In particular, we consider a well-studied reconfiguration model which consists of a rectangular array of PEs with spare columns of PEs on one side. In the presence of faulty PEs, reconfiguration is achieved by constructing alogical array using only the healthy non-spare and spare PEs. Note that one can always successfully reconfigure the array as long as the number of faulty PEs is no more than the number of spare PEs. The general objective, however, is to derive a logical array such that the geometric distances betweenlogical neighbors (i.e., PEs that are connected in the reconfigured array) are kept small. This criterion is motivated by the fact that shorter interconnects reduce the communication delays among the PEs, and also lead to less routing hardware. The problem of determining a reconfiguration that minimizes the length of the longest interconnect ishard and several researchers have presented sub-optimal algorithms that seem to have satisfactory performance. In this paper we develop anew efficient algorithm that can reconfigure any array with arbitrary patterns of faulty PEs. Furthermore we show that our algorithm performs better than most of the other algorithms developed for similar models.

Regular processor arrays for matrix algorithms with pivoting

It is shown how to obtain regular (though nonsystolic) processor arrays for algorithms with pivoting. First, the fact that pivoting algorithms cannot be systolic is established. Then it is shown how regular iterative algorithms can be formulated for the Gaussian elimination algorithm with partial pivoting and how the algorithm can then be implemented on the so-called regular iterative arrays (locally connected arrays of essentially identical processor modules, with register pipelines and/or LIFO (last-in/first-out) buffers in some of the links).<<ETX>>