Jonathan W. Greene

An architecture for electrically configurable gate arrays

An architecture for electrically configurable gate arrays using a two-terminal antifuse element is described. The architecture is extensible, and can provide a level of integration comparable to mask-programmable gate arrays. This is accomplished by using a conventional gate array organization with rows of logic modules separated by wiring channels. Each channel contains segmented wiring tracks. The overhead needed to program the antifuses is minimized by an addressing scheme that utilizes the wiring segments, pass transistors between adjacent segments, shared control lines, and serial addressing circuitry at the periphery of the array. This circuitry can also be used to test the device prior to programming and observe internal nodes after programming. By providing sufficient wiring tracks segmented into carefully chosen lengths and a logic module with a high degree of symmetry, fully automated placement and routing is facilitated. >

An FPGA family optimized for high densities and reduced routing delay

The Act-2 family of CMOS field-programmable gate arrays (FPGAs) uses an electrically programmable antifuse and novel architectural and circuit features to obtain higher logic densities while increasing speed and routability. Improvements include: two new logic modules, novel I/O and clock driver circuitry, and more flexible and faster routing paths. New addressing circuitry shortens programming time and speeds complete testing for shorts, opens, and stuck-at faults. Fully automatic placement and complete routing are retrained. Special software tools used for architectural exploration and layout generation are discussed.<<ETX>>

A CMOS 32b Wallace tree multiplier-accumulator

A 32b integer multiplier-accumulator chip with 56ns cycle time will be described. Automated placement, routing and cell compilation was used on a 2μm CMOS IC which dissipates 1W.

Segmented channel routing

Novel problems concerning routing in a segmented routing channel are introduced. These problems are fundamental to routing and design automation for field programmable gate arrays (FPGAs), a new type of electrically programmable VLSI. The first known theoretical results on the combinatorial complexity and algorithm design for segmented channel routing are presented. It is shown that the segmented channel routing problem is in general NP-complete. Efficient polynomial time algorithms for a number of important special cases are presented. >

Improving Simulated Annealing-Based FPGA Placement With Directed Moves

Simulated annealing remains a widely used heuristic for field-programmable gate array placement due, in part, to its ability to produce high-quality placements while accommodating complex objective functions. This paper discusses enhancements to annealing-based placement which improve upon both quality and run-time. Specifically, intelligent strategies for selecting and placing cells are interspersed with traditional random moves during an anneal, allowing the annealer to converge more quickly and to attain better quality with less statistical variability. For the same amount of computational effort, the contributions discussed in this paper consistently improve both critical path delay and wire length compared to traditional annealing perturbations.

Area and Delay Penalties in Restructurable Wafer-Scale Arrays

The penalties for restructuring wafer-scale arrays for yield enhancement are assessed. Each element of the fabricated array is assumed to be defective with independent probability p. A fixed fraction R of the elements are to be connected into a prespecified defect-free configuration by means of switched interconnections. The area penalty is determined by the required number of tracks per wiring channel t. Propagation delay is determined by the required maximum connection length d. It is shown that: Connection of RN fixed I/O ports to distinct nondefective elements from an N-element linear array requires d, t =θ(logN); Connection of RN pairs of elements from two N-element linear arrays requires only constant d and t; Connection of a chain of RN 2 elements from an N×N array also requires only constant d and t; Connection of a \(\sqrt R N \times \sqrt R N\) lattice from an N×N array requires \(d = \Omega (\sqrt {\log N} )\). Constant t suffices to connect a lattice if d=θ(logN). Algorithms are presented that connect any fraction R < l-p of the elements with probability approaching one as N increases. It appears that these results hold even under actual defect distributions.

A 65nm flash-based FPGA fabric optimized for low cost and power

This paper describes a non-volatile reprogrammable FPGA fabric, whose configuration data are provided directly by flash memory. The fabric is optimized for low-cost, low-power applications, leveraging the density of flash and the elimination of conventional configuration SRAM and its attendant static power. After surveying the necessary background on flash and its application to FPGAs, the 1T flash cell is described along with relevant novel aspects of the fabric architecture. The addition of a third level of switching between inter-cluster signals and logic inputs helps to reduce area and raise typical utilization above 95%. Despite the longer signal path, performance is maintained by synergism between the improved routing flexibility and extreme minimization of the fastest LUT input delay. Test cost is reduced by built-in circuits that can test all switches without reprogramming the flash memory. The fabric has been implemented in a 65nm CMOS embedded flash process.

Rent's rule based FPGA packing for routability optimization

Packing is a critical step in the CAD flow for cluster-based FPGA architectures, and has a significant impact on the quality of the final placement and routing results. One basic quality metric is routability. Traditionally, minimizing cut (the number of external signals) has been used as the main criterion in packing for routability optimization. This paper shows that minimizing cut is a sub-optimal criterion, and argues to use the Rent characteristic as the new criterion for FPGA packing. We further propose using a recursive bipartitioning-based k-way partitioner to optimize the Rent characteristic during packing. We developed a new packer, PPack2, based on this approach. Compared to T-VPack, PPack2 achieves 35.4%, 35.6%, and 11.2% reduction in wire length, minimal channel width, and critical path delay, respectively. These improvements show that PPack2 outperforms all previous leading packing tools (including iRAC, HDPack, and the original PPack) by a wide margin.

Post-placement interconnect entropy: how many configuration bits does a programmable logic device need?

We introduce the concept of post-placement interconnect entropy: the minimal number of bits required to describe a well-placed netlist, which has connection lengths distributed according to Rents rule. The entropy is a function of the number N of cells in the netlist and the Rent exponent p. We derive an expression for the entropy per cell and show that it converges as N approaches infinity. The entropy provides an achievable lower bound on the number of configuration bits in a programmable logic device. Specific numerical values are computed for practical situations. For example, any scalable FPGA composed of 4-input lookup table cells would require 31 configuration bits per cell. We compare this to the actual number of configuration bits in a standard FPGA architecture. We generalize the bound to dimensions higher than two, and show that for any p there is an optimal dimension that minimizes the bound.

Technology Mapping into General Programmable Cells

Field-Programmable Gate Arrays (FPGA) implement logic functions using programmable cells, such as K-input lookup-tables (K-LUTs). A K-LUT can implement any Boolean function with K inputs and one output. Methods for mapping into K-LUTs are extensively researched and widely used. Recently, cells other than K LUTs have been explored, for example, those composed of several LUTs and those combining LUTs with several gates. Known methods for mapping into these cells are specialized and complicated, requiring a substantial effort to evaluate custom cell architectures. This paper presents a general approach to efficiently map into single-output K-input cells containing LUTs, MUXes, and other elementary gates. Cells with to 16 inputs can be handled. The mapper is fully automated and takes a logic network and a symbolic description of a programmable cell, and produces an optimized network composed of instances of the given cell. Past work on delay/area optimization during mapping is applicable and leads to good quality of results.