W. K. Liu

Ultrahigh-Speed 0.5 V Supply Voltage

The direct epitaxial growth of ultrahigh-mobility InGaAs/InAlAs quantum-well (QW) device layers onto silicon substrates using metamorphic buffer layers is demonstrated for the first time. In this letter, 80 nm physical gate length depletion-mode InGaAs QW transistors with saturated transconductance gm of 930 muS / mum and fT of 260 GHz at VDS = 0.5 V are achieved on 3.2 mum thick buffers. We expect that compound semiconductor-based advanced QW transistors could become available in the future as very high-speed and ultralow-power device technology for heterogeneous integration with the mainstream silicon CMOS.

\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}

A direct growth approach using composite metamorphic buffers was employed for monolithic integration of InP-based high electron mobility transistors (HEMTs) and heterojunction bipolar transistors (HBTs) on Ge and Ge-on-insulator (GeOI)/Si substrates using molecular beam epitaxy. GaAs layers nucleated on these substrates and grown to a thickness of 0.5μm were optimized to minimize the nucleation and propagation of antiphase boundaries and threading dislocations, and exhibited an atomic force microscopy rms roughness of ∼9A and x-ray full width at half maximum of ∼36arcsec. A 1.1μm thick graded InAlAs buffer was used to transition from the GaAs to InP lattice parameters. The density of threading dislocations at the upper interface of this InAlAs buffer was ∼107cm−2 based on cross-sectional transmission electron microscopy analyses. HEMT structures grown metamorphically on GeOI/Si substrates using these buffer layers demonstrated transport properties equivalent to base line structures grown on InP substrates...

Quantum-Well Transistors on Silicon Substrate

The structural, morphological, defect properties, and OFF state leakage current mechanism of mixed As-Sb type-II staggered gap GaAs-like and InAs-like interface heterostructure tunnel field effect transistors (TFETs) grown on InP substrates using linearly graded InxAl1-xAs buffer by molecular beam epitaxy are investigated and compared. Symmetric relaxation of >90% and >75% in the two orthogonal 〈110〉 directions with minimal lattice tilt was observed for the terminal GaAs0.35Sb0.65 and In0.7Ga0.3As active layers of GaAs-like and InAs-like interface TFET structures, respectively, indicating that nearly equal numbers of α and β dislocations were formed during the relaxation process. Atomic force microscopy reveals extremely ordered crosshatch morphology and low root mean square roughness of ∼3.17 nm for the InAs-like interface TFET structure compared to the GaAs-like interface TFET structure of ∼4.46 nm at the same degree of lattice mismatch with respect to the InP substrates. The GaAs-like interface exhibit...

Molecular beam epitaxy growth of metamorphic high electron mobility transistors and metamorphic heterojunction bipolar transistors on Ge and Ge-on-insulator/Si substrates

We present results on the direct monolithic integration of III–V devices and Si CMOS on a silicon substrate. InP HBTs (0.5 × 5 um2 emitter) with ft and fmax ≫ 200GHz were grown directly in windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices Engineered Substrates). A BCB based multilayer interconnect process was used to interconnect the InP HBT and Si CMOS to create a differential amplifier demonstration circuit. The heterogeneously integrated differential amplifier serves as the building block for high speed, low power dissipation mixed signal circuits such as ADCs and DACs.

Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy

We demonstrate synthesis of p-channel InSb MOSFET with 1.9% compressive biaxial strain with outstanding room temperature and 150K Hall mobility of 680 cm2/Vs and 2,500 cm2/Vs at hole sheet density of 5x1012 /cm2 and 2.3x1012 /cm2, respectively. The incorporation of an InP layer on top of Al0.35In0.65Sb barrier allows for integration of a high-k dielectric and demonstration of InSb pMOSFET with significantly reduced gate leakage. Parallel conduction limits the on-off ratio of the InSb MOSFET above 150K. Refinement of the InP barrier to reduce interface states and buffer layer to reduce parallel conduction is expected to improve InSb pMOSFET characteristics at 300K.

A high performance differential amplifier through the direct monolithic integration of InP HBTs and Si CMOS on silicon substrates

We present results on the direct monolithic integration of III–V devices and Si CMOS on a silicon substrate. Through optimization of device fabrication and material growth processes III–V devices with electrical performance comparable to devices grown on native III–V substrates were grown directly in windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices Engineered Substrates). While the results presented here are for InP HBTs, our direct heterogeneously integration approach is equally applicable to other III–V electronic (FETs, HEMTs) and opto-electronic (photodiodes, VSCLS) devices and opens the door to a new class of highly integrated, high performance, mixed signal circuits.

Compressively strained InSb MOSFETs with high hole mobility for p-channel application

GaAs pseudomorphic high electron mobility transistor (PHEMT) structures were grown by molecular beam epitaxy on germanium substrates and composite silicon template wafers incorporating silicon and germanium transferred layers. Windows were etched down to the buried germanium layer and subsequent blanket material growth resulted in single crystal growth in the windows and polycrystalline growth on the top SiO2 surface. Wire growth was eliminated at the window edges and on the top SiO2 surface. Secondary ion mass spectrometry measurements and transmission electron micrographs of GaAs grown on germanium indicated an abrupt GaAs–Ge interface with little penetration of antiphase boundaries or other defects into the GaAs layer. For PHEMT material grown on silicon template wafers, a surface roughness of 8 A was measured by atomic force microscopy. The room temperature photoluminescence intensity of the InGaAs channel in the PHEMT structure was equivalent to that grown on GaAs substrates. Measured PHEMT mobilitie...

Progress and challenges in the direct monolithic integration of III–V devices and Si CMOS on silicon substrates

Four in. (100mm)-diameter semi-insulating InP substrates from multiple suppliers were evaluated and compared in terms of their epiready crystal quality and surface properties as required for growth in a multiwafer molecular-beam epitaxy system. All epiwafers in this work exhibited excellent crystalline and structural properties. The postgrowth surface morphology and defect density were typically within standard expectations; however, some fallout was observed due to variations in surface finish. Upon investigation of epilayer-substrate interfacial properties, significant differences were observed between the various vendors and also within substrate lots from individual vendors. While some substrates exhibited a clean interface, others had n-type charge accumulations of varying magnitudes. The interface contamination, silicon or sulfur arising from the substrate surface preparation process or from the substrate packaging, resulted in poor device isolation. Buffer leakage currents were proportional to the ...

Molecular beam epitaxial growth and properties of GaAs pseudomorphic high electron mobility transistors on silicon composite substrates

The thermal budget/integration challenges for SOLES have been investigated. A process window has been found that allows for the successful demonstration of a monolithically integrated III-V/Si differential amplifier. A method of increasing the integration flexibility of SOLES by introducing SiNx interlayers has been demonstrated. Future work will explore the increased thermal budget/integration flexibility of SOLES provided by incorporating embedded GaAs layers.

Comparative studies of the epireadiness of 4in. InP substrates for molecular-beam epitaxy growth

We summarize our work on creating substrate platforms, processes, and devices for the monolithic integration of silicon CMOS circuits with III-V optical and electronic devices. Visible LEDs and InP HBTs have been integrated on silicon materials platforms that lend themselves to process integration within silicon fabrication facilities. We also summarize research on tensile Ge, which could be a high mobility material for III-V MOS, and research on an in-situ MOCVD Al2O3/GaAs process for III-V MOS.