W. R. Davis

Demystifying 3D ICs: the pros and cons of going vertical

This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rents rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-/spl mu/m technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-/spl mu/m through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.

A design environment for high throughput, low power dedicated signal processing systems

A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented. A modular framework based on a combined Simulink and floorplan description drives automatic layout generation. Automatic characterization of layout improves system-level estimates. The flow is demonstrated on the subsystems of CDMA and OFDM receivers and a 300 k transistor test-chip.

A 500-Mb/s soft-output Viterbi decoder

Two 8-state, 7-bit soft output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in 0.18µm CMOS technology. Architectural transformation of the add-compare-select structures and modification of the register exchange allow a high throughput with small area overhead. The 4mm2chip has been verified to decode at 500Mb/s with 1.8V supply. These decoders are used with Turbo codes, which have been demonstrated to achieve information rates very close to the Shannon limit.

The Robertson-Walker metric and the symmetries belong to the family of contracted Ricci collineations

It is shown that the general form of the Robertson-Walker cosmological metric admits symmetry properties that are members of the symmetry family of contracted Ricci collineations. A particular form for the conservation law generator given by ▽j[(−g)1/2(Tij−1/2δijT)ηi] = 0 following in consequence of these symmetries is obtained and interpreted.

Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring

The degraded thermal path of 3-D integrated circuits (3DICs) makes thermal analysis at the chip-scale an essential part of the design process. Performing an appropriate thermal analysis on such circuits requires a model with junction-level fidelity; however, the computational burden imposed by such a model is tremendous. In this paper, we present enhancements to two thermal modeling techniques for integrated circuits to make them applicable to 3DICs. First, we present a resistive mesh-based approach that improves on the fidelity of prior approaches by constructing a thermal model of the full structure of 3DICs, including the interconnect. Second, we introduce a method for dividing the thermal response caused by a heat load into a high fidelity “near response” and a lower fidelity “far response” in order to implement Power Blurring high definition (HD), a hierarchical thermal simulation approach based on Power Blurring that incorporates the resistive mesh-based models and allows for junction-level accuracy at the full-chip scale. The Power Blurring HD technique yields approximately three orders of magnitude of improvement in memory usage and up to six orders of magnitude of improvement in runtime for a three-tier synthetic aperture radar circuit, as compared to using a full-chip junction-scale resistive mesh-based model. Finally, measurement results are presented showing that Power Blurring high definition (HD) accurately determines the shape of the thermal profile of the 3DIC surface after a correction factor is added to adjust for a discrepancy in the absolute temperature values.

Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies

3-D stacking and integration can provide system advantages. This paper explores application drivers and computer-aided design (CAD) for 3-D integrated circuits (ICs). Interconnect-rich applications especially benefit, sometimes up to the equivalent of two technology nodes. This paper presents physical-design case studies of ternary content-addressable memories (TCAMs), first-in first-out (FIFO) memories, and a 8192-point fast Fourier transform (FFT) processor in order to quantify the benefit of the through-silicon vias in an available 180-nm 3-D process. The TCAM shows a 23% power reduction and the FFT shows a 22% reduction in cycle-time, coupled with an 18% reduction in energy per transform.

Implementation of high throughput soft output Viterbi decoders

The architectural considerations for VLSI implementations of soft output Viterbi decoders are presented. Structural transformation of the add-compare-select structures provides high throughput with small area overhead. Modifications to the survivor memory unit and a comparison between the register exchange and memory traceback methods are highlighted. A 4 mm/sup 2/ demonstration chip, consisting of two parallel, 8-state, 7-bit soft output Viterbi decoders, has been implemented in 0.18 /spl mu/m CMOS technology, and decodes at 500 Mb/s with 1.8 V supply. These decoders are used with turbo codes, which have been demonstrated to achieve information rates close to the Shannon limit.

Mechanical Conservation Laws and the Physical Properties of Groups of Motions in Flat and Curved Space-Times

The intimate relation of symmetry properties describable by groups of motions and the consequent conservation laws realizable for a particle in classical mechanics and in the mechanics of restricted and general theories of relativity are discussed in detail using elementary results of the theory of continuous groups. In addition, for the case of special relativistic mechanics the finite form of the groups of motions, underlying all of the possible constants of the motion of the form of first integrals linear in the momenta, are constructed and shown to be the inhomogeneous (i.e., including displacements) proper Lorentz transformations.

Groups of Curvature Collineations in Riemannian Space‐Times Which Admit Fields of Parallel Vectors

By definition, a Riemannian space Vn admits a symmetry called a curvature collineation (CC) if the Lie derivative with respect to some vector ξi of the Riemann curvature tensor vanishes. It is shown that if a Vn admits a parallel vector field, then it will admit groups of CCs. It follows that every space‐time with an expansion‐free, shear‐free, rotation‐free, geodesic congruence admits groups of CCs, and hence gravitational pp waves admit such groups of symmetries.

Inter-die signaling in three dimensional integrated circuits

This work discusses a three dimensional network on chip (3D NoC) fabricated in the 0.18 mum MIT Lincoln Laboratories 3D FDSOI 1.5 V process. As a proof of concept, a three tier, 27 node, NoC test chip occupying 4 mm2 per tier was designed and tested. It is the first of its kind to demonstrate successful inter-tier signaling in a complex three dimensional design, and validates the technology as a viable alternative to the continued scaling of conventional CMOS processes. Simulated results show that when implemented in this 3D process, simple 3D mesh interconnection networks allow for the sharing of global routing resources for complex systems while consuming an extremely low 2 mW of power per transaction. Using these results, we establish the need for a 3D network simulator to quantify the advantage 3D circuit implementations have over 2D.