Paul D. Franzon

Demystifying 3D ICs: the pros and cons of going vertical

This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rents rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-/spl mu/m technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-/spl mu/m through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.

A review of 3-D packaging technology

This paper reviews the state-of-the-art in three-dimensional (3-D) packaging technology for very large scale integration (VLSI). A number of bare dice and multichip module (MCM) stacking technologies are emerging to meet the ever increasing demands for low power consumption, low weight and compact portable systems. Vertical interconnect techniques are reviewed in detail. Technical issues such as silicon efficiency, complexity, thermal management, interconnection density, speed, power etc. are critical in the choice of 3-D stacking technology, depending on the target application, and are briefly discussed.

An electronically tunable microstrip bandpass filter using thin-film Barium-Strontium-Titanate (BST) varactors

A tunable third-order combline bandpass filter using thin-film barium-strontium-titanate varactors and fabricated on a sapphire substrate is reported. Application of 0-200-V bias varied the center frequency of the filter from 2.44 to 2.88 GHz (16% tuning) while achieving a 1-dB bandwidth of 400 MHz. The insertion loss varied from 5.1 dB at zero bias to 3.3 dB at full bias, while the return loss exceeded 13 dB over the range. The third-order intercept of the filter was found to be 41 dBm.

FreePDK: An Open-Source Variation-Aware Design Kit

This paper discusses an open source, variation aware Process Design Kit (PDK), based on Scalable CMOS design rules, down to 45 nm,for use in VLSI research, education and small businesses. This kit includes all the necessary layout design rules and extraction command decks to capture layout dependent systematic variation and perform statistical circuit analysis. The kit also includes a standard cell and pad library with the necessary support files to enable full chip place and route and verification for System on Chip designs. Test chips designed with this PDK are designed in such a way so that they can be fabricated by fabrication facilities allowing validation of the design rules so that the rules may be used in future multi-project runs and design contests.

Configurable string matching hardware for speeding up intrusion detection

Signature-based Intrusion Detection Systems (IDSs) monitor network traffic for security threats by scanning packet payloads for attack signatures. IDSs have to run at wire speed and need to be configurable to protect against emerging attacks. In this paper we consider the problem of string matching which is the most computationally intensive task in IDS. A configurable string matching accelerator is developed with the focus on increasing throughput while maintaining the configurability provided by the software IDSs. Our preliminary results suggest that the hardware accelerator offers an overall system performance of up to 14Gbps.

Nanocell logic gates for molecular computing

Molecular electronics seeks to build electrical devices to implement computation - logic and memory - using individual or small collections of molecules. These devices have the potential to reduce device size and fabrication costs, by several orders of magnitude, relative to conventional CMOS. However, the construction of a practical molecular computer will require the molecular switches and their related interconnect technologies to behave as large-scale diverse logic, with input/output wires scaled to molecular dimensions. It is unclear whether it is necessary or even. possible to control the precise regular placement and interconnection of these diminutive molecular systems. This paper describes genetic algorithm-based simulations of molecular device structures in a nanocell where placement and connectivity of the internal molecular switches are not specifically directed and the internal topology is generally disordered. With some simplifying assumptions, these results show that it is possible to use easily fabricated nanocells as logic devices by setting the internal molecular switch states after the topological molecular assembly is complete. Simulated logic devices include an inverter, a NAND gate, an XOR gate and a 1-bit adder. Issues of defect and fault tolerance are addressed.

Energy consumption modeling and optimization for SRAM's

The recent trends in portable computing technologies have established the need for energy efficient design strategies. To achieve minimum energy design goals, system designers need a technique to accurately model the energy consumption of their design alternatives without performing a full physical design and full-circuit simulation. This paper presents and compares five approaches for modeling the energy consumption of CMOS circuits. These five modeling approaches have been chosen to represent the various levels of model complexity and accuracy found in the current literature. These modeling approaches are applied to the energy consumption of SRAMs to provide examples of their use and to allow for the comparison of their modeling qualities. It was found that a mixed characterization model-using a CV/sup 2/ prediction for digital subsections and fitted simulation results for the analog subsections-is satisfactory (within /spl plusmn/1 process variation) for predicting the absolute energy consumed per cycle. This same model is also very good (within 2%) for predicting an optimum organization for the internal structures of the SRAM. Several common architectures and circuit designs for SRAMs are analyzed with these models. This analysis shows that global, rather than local improvements, produce the largest energy savings. >

Demystifying Surrogate Modeling for Circuits and Systems

In this article, grey-box and black-box surrogate modeling are described, with some key findings. The important point is that surrogate modeling has a solid mathematical basis leading to what has become a dramatic increase in our ability to develop engineering models and to engineer systems. In Section 2, a systematic approach to constructing surrogate models is provided. Each step is explained using published methods. Section 3 presents surrogate modeling examples from the domain of circuits and systems.

4 Gbps high-density AC coupled interconnection

AC coupled interconnects enable multi-gigabit-persecond communication data rates between integrated circuits with very high pin counts and low power consumption. AC coupling can be realized with either series capacitive or inductive coupling elements. Capacitive AC coupling offers better performance when low power I/O buffers are required and when there is sufficient area to dedicate to coupling capacitors in the top-level metal of each IC. At a slight expense of circuit complexity, inductive AC coupling can be used to bring I/O pad pitches down to 75 /spl mu/m and maintain a controlled impedance connection. A novel physical structure, buried solder bumps, are used as a solution for providing DC power and ground connections across the same surface as the AC connections. When used in conjunction with NRZ-tolerant receivers, and current-mode signaling, highly effective interconnect structures can be built. As well as presenting both physical and circuit aspects of this work, experimental results are shown.

3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver

A 120-mV/sub ppd/ low swing pulse receiver is presented for AC coupled interconnect (ACCI). Using this receiver, 3Gb/s chip-to-chip communication is demonstrated through a wire-bonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines. A test chip was fabricated in TSMC 0.18-/spl mu/m CMOS technology and the driver and pulse receiver dissipate 15-mW power per I/O at 3 Gb/s, with a bit error rate less than 10/sup -12/. First-time demonstration of a flip-chip ACCI is also presented, with both the AC and DC connections successfully integrated between the flipped chip and the multichip module (MCM) substrate by using the buried bump technology. For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate.