Wang Lunyao

A universal asynchronous receiver transmitter design

In this paper, a UART design is proposed. The design has an auto-tuning baud rate generator. For achieving the speed matching of the processor and UART interface, it takes asynchronous FIFOs as buffers to realize data exchange between UART and external devices. The whole design is functionally verified using ModelSim SE 6.0, and synthesized and optimized by Synplicitys Synplify Premier 9.6.2.

Dual-V th based double-edge explicit-pulsed level-converting flip-flops

Clustered voltage scaling (CVS) systems is an efficient power reduction technique. One of the design challenges in CVS is the efficient level-converting flip-flop (LCFF) with less overhead in power and delay. In this paper, a level converting flip-flop based pass-transisor logic (LCFFBPT) and a static level converting flip-flop (SLCFF) are proposed, respectively. In addition, the two level-converting flip-flops can leverage availability of a second Vth to maintain good speed characteristics and less leakage power consumption. In the terms of the power delay product (PDP), based on simulation results using HSPICE in 45nm CMOS technology, the proposed flip-flops exhibit up to 68% reduction compared to existing level-converting flip-flops.

A fast algorithm for multi-level mixed-polarity Reed-Muller functions optimization

In this paper, an effective strategy of extraction of common variables from onset table is proposed. By employing the strategy, a novel algorithm is presented to derive a compact multi-level mixed-polarity Reed-Muller expression. The experiment results show that the proposed algorithm can significantly reduce the literals of the RM functions. Compared with published results, the proposed algorithm works faster and needs less memory.

Level Converting Scan Flip-Flop

Clustered voltage scaling (CVS) is an effective way to decrease power dissipation in nanoscale circuit design. One of the design challenges in the CVS is the design of an efficient level converting flip-flop with fewer power and delay overheads. In this paper, we present the static level converting scan flip-flop (SLCSFF), which employs clock and power gating during idle mode to eliminate dynamic power and reduce static power, while retaining its state. The dual-edge triggering capability is achieved by using a dual pulse clock generator that generates short pulses at both rising and falling edges of the clock. Based on simulation results in a 45nm CMOS technology, the proposed level converting scan flip-flop outperforms the existing ones by 56%-75% in terms of Power-Delay Product (PDP).

Dual logic and its application in logic minimization

Based on the logic detection technique, a cover of a logic function is divided into two sections. One is for Boolean logic implementation and the other is for Reed-Muller logic implementation. Comparing to these minimization methods which using either Boolean logic or Reed-Muller logic only, the proposed method using dual logic produces less products. The proposed minimization method is implemented in C and tested on MCNC benchmarks.

Logic detection algorithm for dual logic implementations based on majority cubes

Based on the disjointed cubes of the logic functions, a method by searching majority cubes and Hamming distance to detect logic functions suitable for XOR logic implementation is presented. Some special covers of functions which meet the majority cubes will be expressed as a m-dimension cube and other offset cubes. After majority cubes searching, another logic detection method with hamming distance is used to incorporate those products whose hamming distances are 1 or 2. The proposed algorithm is implemented in C and tested on MCNC benchmarks. The experimental results show that the proposed algorithm is efficient compared with published results.

Detection and decomposition algorithm for dual logic implementations

Based on the disjointed cubes of the logic functions, a method using hamming distance to detect logic functions suitable for Reed-Muller(RM) logic implementation is presented. And the original covers of the logic functions are decomposed into two parts. One is suitable for RM logic implementation and the other is suitable for Boolean logic implementation. The proposed algorithm is implemented in C and tested on MCNC benchmarks. The experimental results show that the proposed algorithm is efficient compared with published methods.

EFFICIENT IMPLEMENTATION OF 3D FILTER FOR MOVING OBJECT EXTRACTION

In this paper the design and implementation of Multi-Dimensional (MD) filter, particularly 3-Dimensional (3D) filter, are presented. Digital (discrete domain) filters applied to image and video signal processing using the novel 3D multirate algorithms for efficient implementation of moving object extraction are engineered with an example. The multirate (decimation and/or interpolation) signal processing algorithms can achieve significant savings in computation and memory usage. The proposed algorithm uses the mapping relations of z-transfer functions between non-multirate and multirate mathematical expressions in terms of time-varying coefficient instead of traditional polyphase decomposition counterparts. The mapping properties can be readily used to efficiently analyze and synthesize MD multirate filters.