Wang Ziqiang

A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth

A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 μm CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm–C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mW for Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide −10 to +40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

A low cost integrated transceiver for mobile UHF passive RFID reader applications

A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18- m CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output P1dB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 2.5mm 2

Wireless receiver architectures for SOC

This paper presents an overview of wireless receiver architectures. It emphasizes the configuration suitable for integration on single chip. It analyzes the advantages and disadvantages of several classical and modern structures and summaries their improvements.This paper presents an overview of wireless receiver architectures. It emphasizes the configuration suitable for integration on single chip. It analyzes the advantages and disadvantages of several classical and modern structures and summaries their improvements.

A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors

A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch, a symmetrical readout circuit is realized. The linear input range is increased, and the systematic offsets of two input op-amps are cancelled. The common-mode noise and even-order distortion are also rejected. A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps, and a Verilog-A-based varactor is used to model the real variable sensing capacitor. Simulation results show that the output voltage of this proposed readout circuit responds correctly, while the under-test capacitance changes with a frequency of 1 kHz. A metal-insulator-metal capacitor array is designed on chip for measurement, and the measurement results show that this circuit achieves sensitivity of 370 mV/pF, linearity error below 1% and power consumption as low as 2.5 mW. This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.

VLSI design of spread spectrum encoding low power RFID tag baseband processor

Due to the weak signal energy of the backscatter link, traditional RFID communication is easily affected by noises, interferences, and interceptions from the environment. To solve the problem, a novel passive UHF RFID tag baseband processor enhanced with spread spectrum technique is presented in this paper. In addition, power-saving strategies are proposed to reduce the power consumption of the tag. Simulated results show that spread spectrum approach largely reduces the Bit Error Rate and improves systems reliability and security. Finally, a complete RFID tag with the proposed baseband processor was designed and fabricated using 0.18um 1P6M CMOS technology. From the measurement result, the overall power consumption of the baseband processor is about 8.8uW at the minimum voltage of 1.04V.