Zheng Xuqiang

An S/H circuit with parasitics optimized for IF-sampling*

An IF-sampling S/H is presented, which adopts a flip-around structure, bottom-plate sampling technique and improved input bootstrapped switches. To achieve high sampling linearity over a wide input frequency range, the floating well technique is utilized to optimize the input switches. Besides, techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance. The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit, 250 MS/s pipeline ADC. For 30 MHz input, the measured SFDR/SNDR of the ADC is 94.7 dB/68. 5dB, which can remain over 84.3 dB/65.4 dB for input frequency up to 400 MHz. The ADC presents excellent dynamic performance at high input frequency, which is mainly attributed to the parasitics optimized S/H circuit.

Self-calibrating on-chip termination resistor for high-speed SerDes

A digital tuning self-calibrating on-chip termination resistor for high-speed SerDes is presented in this paper. An offchip reference resistor is used to adjust the on-chip resistor automatically through feedback. SAR logic is used for tuning, which shorts the tuning time. Special analog design is used to eliminate the offset of circuit and reduce the power consumption.