Wanjun Chen

High-performance AlGaN∕GaN lateral field-effect rectifiers compatible with high electron mobility transistors

A high electron mobility transistor (HEMT)-compatible power lateral field-effect rectifier (L-FER) with low turn-on voltage is demonstrated using the same fabrication process as that for normally off AlGaN∕GaN HEMT, providing a low-cost solution for GaN power integrated circuits. The power rectifier features a Schottky-gate-controlled two-dimensional electron gas channel between the cathode and anode. By tying up the Schottky gate and anode together, the forward turn-on voltage of the rectifier is determined by the threshold voltage of the channel instead of the Schottky barrier. The L-FER with a drift length of 10μm features a forward turn-on voltage of 0.63V at a current density of 100A∕cm2. This device also exhibits a reverse breakdown voltage (BV) of 390V at a current level of 1mA∕mm and a specific on resistance (RON,sp) of 1.4mΩcm2, yielding a figure of merit (BV2∕RON,sp) of 108MW∕cm2. The excellent device performance, coupled with the lateral device structure and process compatibility with AlGaN∕GaN...

Single-Chip Boost Converter Using Monolithically Integrated AlGaN/GaN Lateral Field-Effect Rectifier and Normally Off HEMT

We demonstrate a single-chip switch-mode boost converter that features a monolithically integrated lateral field-effect rectifier (L-FER) and a normally off transistor switch. The circuit was fabricated on a standard AlGaN/GaN HEMT epitaxial wafer grown with GaN-on-Si technology. The fabricated rectifier with a drift length of 15 mum exhibits a breakdown voltage of 470 V, a turn-on voltage of 0.58 V, and a specific on-resistance of 2.04 mOmegaldrcm2. The L-FER exhibits no reverse recovery current associated with the turn-off transient because of its unipolar nature. A prototype of GaN-based boost converter that includes monolithically integrated rectifiers and transistors is demonstrated using conventional GaN-on-Si wafers for the first time to prove the feasibility of the GaN-based power IC technology.

High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

A high-voltage lateral double-diffusion MOSFET (LDMOS) with a charge-balanced surface low on-resistance path (CBSLOP) layer is proposed and experimentally demonstrated using a modified CMOS process. The CBSLOP layer can not only provide a low on-resistance path in the on-state but also keep the charge balance between the N and P pillars of a surface low on-resistance path in the off-state, which results in improved breakdown voltage (BV). The experimental results show that the CBSLOP-LDMOS with a drift length of 35 mum exhibits a BV of 500 V and specific on-resistance (<i>R</i> _on, _sp) of 96 mOmega ldr cm², yielding to a power figure of merit (<i>BV</i> ²/ <i>R</i> _on, _sp) of 2.6 MW/cm² . The excellent device performances, coupled with a CMOS-compatible fabrication process, make the proposed CBSLOP-LDMOS a promising candidate for smart power integrated circuit.

A Snapback Suppressed Reverse-Conducting IGBT With a Floating p-Region in Trench Collector

A novel reverse-conducting insulated-gate bipolar transistor (RC-IGBT) featuring an oxide trench placed between the n-collector and the p-collector and a floating p-region (p-float) sandwiched between the n-drift and n-collector is proposed. First, the new structure introduces a high-resistance collector short resistor at low current density, which leads to the suppression of the snapback effect. Second, the collector short resistance can be adjusted by varying the p-float length without increasing the collector cell length. Third, the p-float layer also acts as the base of the n-collector/p-float/n-drift transistor which can be activated and offers a low-resistance current path at high current densities, which contributes to the low on-state voltage of the integrated freewheeling diode and the fast turnoff. As simulations show, the proposed RC-IGBT shows snapback-free output characteristics and faster turnoff compared with the conventional RC-IGBT.

Monolithic integration of lateral field-effect rectifier with normally-off HEMT for GaN-on-Si switch-mode power supply converters

A lateral field-effect rectifier (L-FER) that can be fabricated with normally-off transistor on the same AlGaN/GaN HEMT with the same fabrication process has been demonstrated. The L-FER exhibits low turn-on voltage, low specific on-resistance and high reverse breakdown. A prototype of switch-mode dc-dc boost converter that features monolithically integrated L-FER and normally-off HEMT is demonstrated for the first time using industry-standard GaNon-Si epitaxial wafers to prove the feasibility of GaN power integrated technology.

A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC

In this paper, a novel double RESURF LDMOS with multiple rings in non-uniform drift region is proposed and successfully fabricated. The proposed device maximizes the benefits of the double RESURF technique by optimizes key process and device geometrical parameters in order to achieve the lowest on-resistance with the desired breakdown voltage. In addition, a versatile JFET device is firstly developed. The JFET device cannot only be used as the current detector, but also be used as the internal power supply for SPIC. Besides, it is compatible with Bipolar-CMOS technology, without any additional processes required.

7.6 V Threshold Voltage High-Performance Normally-Off Al 2 O 3 /GaN MOSFET Achieved by Interface Charge Engineering

An efficient approach to engineering the Al₂O₃/GaN positive interface fixed charges by post-dielectric annealing in nitrogen is demonstrated. The remarkable reduction of interface fixed charges from 1.44 × 10¹³ to 3 × 10¹² cm^-2 was observed, which leads to a record high threshold voltage (V_TH) of 7.6 V obtained in the Al₂O₃/GaN MOSFETs. The significantly reduced interface fixed charges and the corresponding remote scattering effect enable respectable improvement in the electron mobility that results in a high drain current density of 355 mA/mm in the device. These competitive results reveal that the method reported in this letter is promising in pushing V_TH more positive and simultaneously achieving good device performance of normally-off GaN power devices.

Integrated Voltage Reference Generator for GaN Smart Power Chip Technology

GaN smart power chip technology has been realized using a GaN-on-Si HEMT platform, featuring monolithically integrated high-voltage power devices and low-voltage peripheral devices for mixed-signal functional blocks. In particular, this brief presents the imperative analog functional block-voltage reference generator for smart power applications with wide-temperature-range stability. The circuit is capable of proper functions within a wide temperature range from room temperature up to 250°C , illustrating the unique advantage of the wide-bandgap GaN in high-temperature operation. The voltage reference generator was designed with an AlGaN/GaN HEMT and Schottky diodes, and the devices were operated in the subthreshold regime to obtain low power consumption. The voltage reference generator achieved an average drift of less than 0.5 mV/°C and can be used as a reference voltage in various biasing and sensing circuits.

Schottky-Contact Technology in InAlN/GaN HEMTs for Breakdown Voltage Improvement

In this paper, we demonstrate a 253% improvement in the off-state breakdown voltage (BV) of the lattice-matched In_0.17Al_0.83 N/GaN high-electron-mobility transistors (HEMTs) by using a new Schottky-contact technology. Based on this concept, the Schottky-source/drain and Schottky-source (SS) InAlN/GaN HEMTs are proposed. The proposed InAlN/GaN HEMTs with an <i>L</i>_GD of 15 μm showed a three-terminal BV of more than 600 V, while the conventional InAlN/GaN HEMTs of the same geometry showed a maximum BV of 184 V. Without using any field plate, the BV of 650 V was measured in the SS InAlN/GaN HEMTs with <i>L</i>_GD = 15 μm, which is the highest BV ever achieved on InAlN/GaN HEMT. The corresponding specific on-resistance (R_sp, _on) is as low as 3.4 mΩ·cm². A BV of 118 V was also obtained in SS InAlN/GaN HEMTs with <i>L</i>_GD = 1 μm, which is the highest BV in GaN-based HEMTs featuring such a short <i>L</i>_GD with GaN buffer. The improvement of the BV relies on the effective suppression of source carrier injection into the GaN buffer under the SS due to the smooth metal morphology and elimination of metal spikes in the Schottky metallization.

High-Voltage SOI SJ-LDMOS With a Nondepletion Compensation Layer

A new superjunction LDMOS on silicon-on-insulator (SOI) with a nondepletion compensation layer (NDCL) is proposed. The NDCL can be self-adaptive to provide additional charges for compensating the charge imbalance while eliminating the substrate-assisted depletion effect. In addition, the high-density oxide interface charges at the top surface of the buried oxide layer (BOX) enhance the electric field in the BOX and improve the vertical breakdown voltage (BV). Numerical simulation results indicate that a uniform surface electric field profile is obtained and that the vertical electric field in BOX is increased to 6 times106 V/cm, which results in a high BV of 300 V for the proposed device with the BOX thickness of 0.5 mum and drift length of 15 mum on a thin SOI substrate.