Wanyeong Jung

An ultra-low power fully integrated energy harvester based on self-oscillating switched-capacitor voltage doubler

This paper presents a fully integrated energy harvester that maintains >35% end-to-end efficiency when harvesting from a 0.84 mm 2 solar cell in low light condition of 260 lux, converting 7 nW input power from 250 mV to 4 V. Newly proposed self-oscillating switched-capacitor (SC) DC-DC voltage doublers are cascaded to form a complete harvester, with configurable overall conversion ratio from 9× to 23×. In each voltage doubler, the oscillator is completely internalized within the SC network, eliminating clock generation and level shifting power overheads. A single doubler has >70% measured efficiency across 1 nA to 0.35 mA output current ( >10 5 range) with low idle power consumption of 170 pW. In the harvester, each doubler has independent frequency modulation to maintain its optimum conversion efficiency, enabling optimization of harvester overall conversion efficiency. A leakage-based delay element provides energy-efficient frequency control over a wide range, enabling low idle power consumption and a wide load range with optimum conversion efficiency. The harvester delivers 5 nW-5 μW output power with >40% efficiency and has an idle power consumption 3 nW, in test chip fabricated in 0.18 μm CMOS technology.

23.3 A 3nW fully integrated energy harvester based on self-oscillating switched-capacitor DC-DC converter

Recent advances in low-power circuits have enabled mm-scale wireless systems [1] for wireless sensor networks and implantable devices, among other applications. Energy harvesting is an attractive way to power such systems due to limited energy capacity of batteries at these form factors. However, the same size limitation restricts the amount of harvested power, which can be as low as 10s of nW for mm-scale photovoltaic cells in indoor conditions. Efficient DC-DC up-conversion at such low power levels (for battery charging) is extremely challenging and has not yet been demonstrated.

IoT design space challenges: Circuits and systems

The Internet of Things (IoT) is a rapidly emerging application space, poised to become the largest electronics market for the semiconductor industry. IoT devices are focused on sensing and actuating of our physical environment and have a nearly unlimited breadth of uses. In this paper, we explore the IoT application space and then identify two common challenges that exist across this space: ultra-low power operation and system design using modular, composable components. We survey recent low power techniques and discuss a low power bus that enables modular design. Finally, we conclude with three example ultra-low power, millimeter-scale IoT systems.

A Dual-Slope Capacitance-to-Digital Converter Integrated in an Implantable Pressure-Sensing System

This work presents a dual-slope capacitance to digital converter for pressure sensing. The design uses base capacitance subtraction with a configurable capacitor bank and dual precision comparators to improve energy efficiency, consuming 110nW with 9.7b ENOB and 0.85pJ/conv·step FoM. The converter is integrated with a pressure transducer, battery, processor, and radio to form a complete 1.4mm×2.8mm×1.6mm sensor system aimed at implantable devices. The system operates from a 3.6V battery.

27.6 A 0.7pF-to-10nF fully digital capacitance-to-digital converter using iterative delay-chain discharge

Capacitance sensors are widely used to measure various physical quantities, including position, pressure, and concentration of certain chemicals [1-6]. Integrating capacitive sensors into a small wireless sensor system is challenging due to their large power consumption relative to the total system power/energy budget, which can be as low as a few nW [4]. Typical capacitance-to-digital converters (CDCs) use charge sharing or charge transfer between capacitors to convert the sampled capacitance to voltage, which is then measured with an ADC [1-6]. This approach requires complex analog circuits, such as amplifiers and ADCs, increasing design complexity and often increasing power consumption. Moreover, the initial capacitance to voltage conversion essentially limits the input capacitance range because of output voltage saturation. This paper presents a fully digital CDC that is based on the observation that when a ring oscillator (RO) is powered from a charged capacitance, the number of RO cycles required to discharge the capacitance to a fixed voltage is naturally linear with the capacitance value. This observation enables a simple, fully digital conversion scheme that is inherently linear. As a result, the proposed CDC performs conversion across a very wide capacitance range from 0.7pF to over 10nF with <; 0.06% linearity error. The CDC senses 11.3pF input capacitance with 35.1 pJ conversion energy and 141fJ/c-s FoM.

15.4b incremental sigma-delta capacitance-to-digital converter with zoom-in 9b asynchronous SAR

An incremental zoom-in capacitance-to-digital converter (CDC) is proposed. By using a 9b SAR, the OSR can be reduced to only 32, significantly improving conversion energy. We show how the OTA in the SAR is bypassed for the CDC further reducing energy and propose a novel matrix based 512-element unit-cap structure for dynamic element matching. The CDC achieves 94.7dB SNR and 33.7μW power consumption with 175fJ/conv-step at 1.4V supply.

27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications

Near-threshold computing (NTC) is an attractive solution to stagnating energy efficiencies in digital integrated circuits, arising from slowed voltage scaling in nanometer CMOS [1-2]. The design of sequential elements for NTC, as well as in voltage-scaled systems operating at both near-threshold and super-threshold, has not been extensively studied. However, it is well known that sequential elements have a strong sensitivity to process variations in NTC [2], which can have a significant impact on system yield and power consumption. In order to achieve reliable energy-efficient operation across a wide operating voltage range, a flip-flop should have the following attributes: 1) static operation, since dynamic nodes are highly susceptible to PVT variations at low voltage; 2) contention-free transitions, since ratioed logic has poor robustness across the wide range of device ION/IOFF ratios incurred with voltage scaling; 3) single-phase clocking, which avoids toggling of internal clock inverters and the corresponding power penalty; 4) minimum or no area penalty compared to conventional flip-flops.

12.1 A rational-conversion-ratio switched-capacitor DC-DC converter using negative-output feedback

Switched-capacitor (SC) DC-DC converters have several advantages over inductive DC-DC converters in that they are easily integrated on-chip and can scale to desired power levels, rendering themselves promising for integrated voltage regulators, especially for small, low-power systems. However, many SC DC-DC converters offer only a few conversion ratios, limiting their use for systems in which either the input or output voltages vary. This is particularly important in wireless systems where battery voltage degrades slowly. [1] proposed a technique to reconfigure cascaded SC converters to achieve arbitrary binary ratios: p/2N, 0<;p<;2N, where N is the number of cascaded stages. This structure was improved in [2] by reversing the cascading order to increase output conductance and in [3] by using a positive feedback approach. However, this design still provides less output conductance than previous works offering only a small fixed number of ratios [4,5]. This paper presents an SC DC-DC converter that can be reconfigured to have any arbitrary rational conversion ratio: p/q, 0<;p<;q≤2N+1. The key idea of the design, which we refer to as a rational DC-DC converter, is to incorporate negative voltage feedback into the cascaded converter stages using negative-generating converter stages (“voltage negators”); this enables reconfiguring of both the numerator p and denominator q of the conversion ratio. With help from the current supply of the voltage negators, output conductance becomes comparable to conventional few-ratio SC DC-DC designs. Hence, the proposed design achieves a resolution higher than previous binary SC converters while maintaining the conversion efficiency of dedicated few-ratio SC converters. Using only 3 cascaded converter stages and 2 voltage negator stages, the rational converter implemented in 0.18μm CMOS offers 79 conversion ratios and achieves >90% efficiency when downconverting from 2V to a 1.1-to-1.86V output voltage range.

A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications

We present an 8-bit sub-ranging SAR ADC designed for bursty signals having long time periods with small code spread. A modified capacitive-DAC (CDAC) saves previous samples MSB voltage and reuses it throughout subsequent conversions. This prevents unnecessary switching of large MSB capacitors as well as conversion cycles, reducing energy consumed in the comparator and digital logic and yielding total energy savings of 2.6×. In 0.18μm CMOS, the ADC consumes 120nW at 0.6V and 100kS/s with 46.9dB SNDR.

8.5 A 60%-efficiency 20nW-500µW tri-output fully integrated power management unit with environmental adaptation and load-proportional biasing for IoT systems

As Internet-of-Things (IoT) systems proliferate, there is a greater demand for small and efficient power management units. Fully integrated switched-capacitor (SC) DC-DC converters are promising candidates due to their small form factor and low quiescent power, aided by dynamic activity scaling [1-3]. However, they offer a limited number of conversion ratios, making them challenging to use in actual systems since they often require multiple output voltages (to reduce power consumption) and use various input power sources (to maximize flexibility). In addition, maintaining both high efficiency and fast load response is difficult at low output current levels, which is critical for IoT devices as they often target low standby power to preserve battery charge. This paper presents a fully integrated power management system that converts an input voltage within a 0.9-to-4V range to 3 fixed output voltages: 0.6V, 1.2V, and 3.3V. A 7-stage binary-reconfigurable DC-DC converter [1-2] enables the wide input voltage range. Three-way dynamic frequency control maintains converter operation at near-optimum conversion efficiency under widely varying load conditions from 5nW to 500μW. A proposed load-proportional bias scheme helps maintain high efficiency at low output power, fast response time at high output power and retains stability across the entire operating range. Analog drop detectors improve load response time even at low output power, allowing the converter to avoid the need for external sleep/wakeup control signals. Within a range of 1-to-4V input voltage and 20nW-500μW output power, the converter shows >60% conversion efficiency, while maintaining responsiveness to a 100× sudden current increase.