Warren A. Hunt

An approach to systems verification

The term systems verification refers to the specification and verification of the components of a computing system, including compilers, assemblers, operating systems and hardware. We outline our approach to systems verification, and summarize the application of this approach to several systems components. These components consist of a code generator for a simple high-level language, an assembler and linking loader, a simple operating system kernel, and a microprocessor design.

Microprocessor design verification

The verification of a microprocessor design has been accomplished using a mechanical theorem prover. This microprocessor, the FM8502, is a 32-bit general-purpose, von Neumann processor whose design-level (gate-level) specification has been verified with respect to its instruction-level specification. Both specifications were written in the Boyer—Moore logic, and the proof of correctness was carried out with the Boyer—Moore theorem prover.

Fast kd-tree Construction with an Adaptive Error-Bounded Heuristic

Construction of effective acceleration structures for ray tracing is a well studied problem. The highest quality acceleration structures are generally agreed to be those built using greedy cost optimization based on a surface area heuristic (SAH). This technique is most often applied to the construction of kd-trees, as in this work, but is equally applicable to the construction of other hierarchical acceleration structures. Unfortunately, SAH-optimized data structure construction has previously been too slow to allow per-frame rebuilding for interactive ray tracing of dynamic scenes, leading to the use of lower-quality acceleration structures for this application. The goal of this paper is to demonstrate that high-quality SAH based acceleration structures can be constructed quickly enough to make them a viable option for interactive ray tracing of dynamic scenes. We present a scanning-based algorithm for choosing kd-tree split planes that are close to optimal with respect to the SAH criteria. Our approach approximates the SAH cost function across the spatial domain with a piecewise quadratic function with bounded error and picks minima from this approximation. This algorithm takes full advantage of SIMD operations (e.g., SSE) and has favorable memory access patterns. In practice this algorithm is faster than sorting-based SAH build algorithms with the same asymptotic time complexity, and is competitive with non-SAH build algorithms which produce lower-quality trees. The resulting trees are almost as good as those produced by a sorting-based SAH builder as measured by ray tracing time. For a test scene with 180 k polygons our system builds a high-quality kd-tree in 0.26 seconds that only degrades ray tracing time by 3.6% compared to a full quality tree

Trace Table Based Approach for Pipeline Microprocessor Verification

This paper presents several techniques for formally verifying pipelined microprocessor implementations that contain out-of-order execution and dynamic resolution of data-dependent hazards. Our principal technique models the trace of executed instructions using a table-based representation called a MAETT. We express invariant properties of pipelined implementations by specifying relations between fields in the MAETT. To show the viability of this technique, we have proved the correctness of a simple out-of-order completion pipelined microprocessor design using the ACL2 theorem prover. This verification was performed incrementally by proving that the specified relations hold for all microarchitectural states reachable from a flushed implementation state, eventually permitting us to prove that the entire pipelined machine design implements its ISA specification.

DRAT-trim: Efficient Checking and Trimming Using Expressive Clausal Proofs

The DRAT-trim tool is a satisfiability proof checker based on the new DRAT proof format. Unlike its predecessor, DRUP-trim, all presently known SAT solving and preprocessing techniques can be validated using DRAT-trim. Checking time of a proof is comparable to the running time of the proof-producing solver. Memory usage is also similar to solving memory consumption, which overcomes a major hurdle of resolution-based proof checkers. The DRAT-trim tool can emit trimmed formulas, optimized proofs, and new TraceCheck + dependency graphs. We describe the output that is produced, what optimizations have been made to check RAT clauses, and potential applications of the tool.

Trimming while checking clausal proofs

Conflict-driven clause learning (CDCL) satisfiability solvers can emit more than a satisfiability result; they can also emit clausal proofs, resolution proofs, unsatisfiable cores, and Craig interpolants. Such additional results may require substantial modifications to a solver, especially if preprocessing and inprocessing techniques are used; however, CDCL solvers can easily emit clausal proofs with very low overhead. We present a new approach with an associated tool that efficiently validates clausal proofs and can distill additional results from clausal proofs. Our tool architecture makes it easy to obtain such results from any CDCL solver. Experimental evaluation shows that our tool can validate clausal proofs faster than existing tools. Additionally, the quality of the additional results, such as unsatisfiable cores, is higher when compared to modified SAT solvers.

Fast and Lazy Build of Acceleration Structures from Scene Hierarchies

In this paper we show how to use structural information about a scene such as is contained in a scene graph to build SAH-based acceleration structures more efficiently. We provide a general method for doing so together with asymptotic analyses for both standard and lazy variants of our method. In particular, we show bounds of O(n) for full k-d tree builds over n primitives and O(v + log n) for lazy k-d tree builds over v visible primitives. We provide experimental results showing that these asymptotic properties translate into real-world speedups. In fact, without a method like ours, it is impossible to achieve better than O(n) for even the first split of a lazy build. We also show that under certain (realistic) assumptions on the scene structure, our method produces provably good acceleration structures. Finally, we provide experimental results demonstrating that our acceleration structures are of nearly indistinguishable quality to those produced with a full SAH build.

Soft irregular shadow mapping: fast, high-quality, and robust soft shadows

We introduce a straightforward, robust, and efficient algorithm for rendering high-quality soft shadows in dynamic scenes. Each frame, points in the scene visible from the eye are inserted into a spatial acceleration structure. Shadow umbrae are computed by sampling the scene from the light at the image plane coordinates given by the stored points. Penumbrae are computed at the same set of points, per silhouette edge, in two steps. First, the set of points affected by a given edge is estimated from the expected light-view screen-space bounds of the corresponding penumbra. Second, the actual overlap between these points and the penumbra is computed analytically directly from the occluding geometry. The umbral and penumbral sources of occlusion are then combined to determine the degree of shadow at the eye-view pixel corresponding to each sample point. An implementation of this algorithm for the Larrabee architecture yields from 27 to 33 frames per second in simulation for scenes from a modern game, and produces significantly higher image quality than other recent methods in the real-time domain.

Ray-specialized acceleration structures for ray tracing

The key to efficient ray tracing is the use of effective acceleration data structures. Traditionally, acceleration structures have been constructed under the assumption that rays approach from any direction with equal probability. However, we observe that for any particular frame the system has significant knowledge about the rays, especially eye rays and hard/soft shadow rays. In this paper we demonstrate that by using this information in conjunction with an appropriate acceleration structure - a set of one or more perspective grids - that ray tracing performance can be significantly improved over prior approaches. This acceleration structure can easily be rebuilt per frame, and provides significantly improved performance for rays originating at or near particular points such as the eye point and the light source(s), without sacrificing the ability to trace arbitrary rays. We demonstrate true real-time frame rates on a game-like scene rendered on an eight-core desktop PC at 1920times1200 resolution for primary visibility, and hard shadows, along with lower frame rates for Monte Carlo soft shadows. In particular, we demonstrate the fastest hard shadow ray-tracing results that we are aware of. We argue that the perspective grid acceleration structure provides insight into why the Z buffer algorithm is faster than traditional ray tracing and shows there is a useful continuum of visibility algorithms between the two traditional approaches.

Processor Verification with Precise Exeptions and Speculative Execution

We describe a framework for verifying a pipelined microprocessor whose implementation contains precise exceptions, external interrupts, and speculative execution. We present our correctness criterion which compares the state transitions of pipelined and non-pipelined machines in presence of external interrupts. To perform the verification, we created a table-based model of pipeline execution. This model records committed and in-flight instructions as performed by the microarchitecture. Given that certain requirements are met by this table-based model, we have mechanically verified our correctness criterion using the ACL2 theorem prover.