Way-Seen Wang

Clockwise C-V hysteresis phenomena of metal--tantalum-oxide--silicon-oxide--silicon ( p) capacitors due to leakage current through tantalum oxide

Thermal tantalum oxide with a thickness of 620 A was studied. The dc leakage resistance and high‐frequency (1‐MHz) resistance of a metal–tantalum‐oxide–silicon capacitor were found to be on the order of 108 and 1 Ω cm2, respectively. The C‐V behavior of the capacitor, with its initial states being carefully treated, was reproduced and observed to be dependent on the return voltage and hold time (at return point) of the measurement conditions. And only negative charges were observed to be responsible for the conduction current through tantalum oxide. A model with the considerations of the ac equivalent circuit and low‐frequency leakage characteristic of tantalum oxide was proposed for these observations. Theoretical examples, with their parameters being suitably given according to the measured data, were shown, and they explained the experimental observations quite well. It is found that the measurement conditions and effect of the ac resistance of tantalum oxide on the determination of flat‐band capacitan...

Residual charges effect on the annealing behavior of Co-60 irradiated MOS capacitors

It was experimentally observed that the residual charges of an MOS capacitor after C-V testing can exist for a long time. These charges include a nonzero field at the SiO/sub 2//Si interface, and subsequently affect the annealing behavior due to a charge-temperature effect if the MOS capacitor is left floating during annealing. This problem is solved by a flat-band condition annealing method based on a charge-temperature technique. The annealing kinetics of a Co-60 irradiated MOS capacitor are then studied. A power-law behavior of the annealing kinetics has been obtained for oxide charges annealed at 300 degrees C. Possible explanations are given for this observation. >

Direct indication of lateral nonuniformities of MOS capacitors from the negative equivalent interface trap density based on charge-temperature technique

The charge-temperature technique was used to investigate the oxide properties of silicon MOS capacitors fabricated on a wafer with an oxide thickness of 660 Å. The stretchout of high frequencyC — V curve of the capacitor after a positive charge-temperature aging was proved to be due to the lateral nonuniformities of mobile charges and the increase of interface traps. The effect of lateral nonuniformitites was found to be successfully described by a model consisting of two parallelly connected nonuniform capacitors. The only parameter of importance is their area ratio, which can be easily determined by theoretical fitting. The appearance of a negative equivalent interface trap density was proposed as a new method to directly identify the existence of lateral nonuniformities.

Characteristics of asymmetrical conductor-backed coplanar waveguides

Abstract Analytical formulae for the quasi-TEM parameters of asymmetrical conductor-backed coplanar waveguides without or with upper shielding are presented. Their accuracy is verified through a comparison between the calculated and the available results for the specially symmetrical case. In addition, the line parameters of each asymmetrical conductor-backed coplanar waveguide are calculated, approximately based on simulating an asymmetrical coplanar line with two symmetrical ones. Good agreement is found for a wide range of geometric parameters.

Single and multiple AlGaAs quantum‐well structures grown by liquid‐phase epitaxy

The Al0.05Ga0.95As/Al0.35Ga0.65As single‐ and multiple‐quantum‐well structures with well widths less than 20 A have been successfully fabricated by liquid‐phase epitaxy using low‐temperature, two‐phase, and dummy wafer methods. The transmission electron microscope cross‐section technique is applied to study the thickness variation of quantum well and the transition width at the heterojunction interface. An interesting phenomenon observed during liquid‐phase epitaxy growth is that the interface of Al0.05Ga0.95As grown on Al0.35Ga0.65As is rather flat and sharp whereas the opposite growth sequence gives rise to a wavy interface. It is believed that the flat Al0.05Ga0.95As/Al0.35Ga0.65As interface is due to a tendency to deposit the epilayer when the Al0.05Ga0.95As solution is in contact with the Al0.35Ga0.65As substrate and the wavy Al0.35Ga0.65As/ Al0.05Ga0.95As interface is due to a tendency to dissolve the substrate when the Al0.35Ga0.65As solution is in contact with the Al0.05Ga0.95As substrate. The tra...

The effect of postoxidation cooling in oxygen on the interface property of MOS capacitors

The interface properties of Al-SiO2-Si(P) capacitors with dry oxides grown at 900°C are studied by cooling the postoxidation samples in an oxygen and nitrogen ambient. Two significant results, which are quite different from the descriptions in the existing literature, occur when the capacitor is negative charge-temperature treated. One is the hysteresis of the C-V curve; the other is the decrease in the number of interface traps. Samples which were cooled in nitrogen only are also examined and compared. The excess oxygen related species near the interface seems to be responsible for these experimental results.

Profile estimation of an implanted‐diffused arsenic layer in silicon

The nonlinear diffusion coefficient of a solid‐state diffusion equation is approximated by a linear function of concentration, and then the resulting diffusion equation is solved exactly by the method of self‐similar solution to obtain a simple expression for the profile estimation of an implanted‐diffused arsenic layer in silicon. This expression is dependent only upon the total implant dose and the initial junction depth, but not the specific form of the initial profile. However, as the diffusion time is long enough, only the total implant dose is of significance. The approximate profile, junction depth, surface concentration, and sheet resistance agree quite well with those obtained by solving the nonlinear diffusion equation numerically or by carrying out the diffusion experimentally.

A study of uv preionization pulsed tea CO2 laser

Abstract A uniform volumetric discharge was obtained by means of an auxiliary UV preionization in a home‐made TEA CO2 laser. The maximum output pulse energy of this laser system was about 12J per pulse with a pulse duration of 80 ns. The ratio of electric field to neutral particle density (E/N) in this laser was 7.6×10‐16 V cm2. The peak power and pulse shape of the laser were studied. The time delay between the predischarge and the maindischarge during the stable operation of this laser system has also been studied. It was observed that the laser was operating with uniform glow discharges when the time delayed between the predischarge and the maindischarge was in the range of 1.0 μs to 6.0 μs. The spark array used as a preionizer for producing the UV radiation in this system is new, simple, durable, and can be easily fabricated.

Direct indication of interface trap states in an MOS capacitor from the peaks of optimal illumination-induced capacitances

Abstract An optical illumination method was used to examine the relationship between the variation of capacitance and the interface trap states of an MOS capacitor after various charge‐temperature agings. The peaks in the illumination‐induced capacitance‐voltage curves were found to be caused neither by the lateral nonuniformities of interface charges nor by the nonuniformities of the illumination intensities, but by the existence of interface trap states. This can be used as a quick method to directly identify the interface trap states.

Constant peak field distribution and voltage dropping in the oxide layer of a MOS capacitor during charge-temperature aging

The newly proposed charge-temperature technique is basically different from the conventional bias-temperature technique. In the former one the total charges on the metal gate are constant, while in the tatter one, the bias voltage across the sample is constant. The peak value of the electric field in the oxide layer of a MOS capacitor is proposed to be constant during charge-temperature aging; and therefore the voltage across the oxide is supposed to be decreased after charge-temperature aging. This assumption is proved to be true experimentally for either positive or negative charge-temperature treatment. Finally, successive charge-temperature agings with the same charging voltage can be regarded as the transition process of bias-temperature aging.