Jenn-Gwo Hwu

Electrical characterization and process control of cost-effective high-k aluminum oxide gate dielectrics prepared by anodization followed by furnace annealing

A cost-effective technique was introduced to prepare ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectrics with equivalent oxide thickness (EOT) down to 14 /spl Aring/. Al/sub 2/O/sub 3/ was fabricated by anodic oxidation (anodization) of ultrathin Al films at room temperature in deionized water and then furnace annealed at 650/spl deg/C in N/sub 2/ ambient. Both dc and dac (dc superimposed with ac) anodization techniques were investigated. Effective dielectric constant of k/spl sim/7.5 and leakage current of 2-3 orders of magnitude lower than SiO/sub 2/ are observed. The conduction mechanism in Al/sub 2/O/sub 3/ gate stack is shown to be Fowler-Nordheim (F-N) tunneling. Saturated current behavior in the inversion region of MOS capacitor is observed. It is found that the saturation current is sensitive to interface state capacitance and can be used as an efficient way to evaluate the Al/sub 2/O/sub 3/ gate stack/Si-substrate interfacial property. An optimal process control for preparing Al/sub 2/O/sub 3/ gate dielectrics with minimized interface state capacitance via monitoring the inversion saturation current is demonstrated.

Ultrathin aluminum oxide gate dielectric on N-type 4H-SiC prepared by low thermal budget nitric acid oxidation

MOS capacitors with an ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric were fabricated on n-type 4H-SiC. Al/sub 2/O/sub 3/ was prepared by room-temperature nitric acid (HNO/sub 3/) oxidation of ultrathin Al film followed by furnace annealing. The effective dielectric constant of k/spl sim/9.4 and equivalent oxide thickness of 26 /spl Aring/ are produced, and the interfacial layer and carbon clusters are not observed in this paper. The electrical responses of MOS capacitor under heating and illumination are used to identify the conduction mechanisms. For the positively biased case, the conduction mechanism is shown to be dominated by Schottky emission with an effective barrier height of 1.12/spl plusmn/0.13 eV. For the negatively biased case, the gate current is shown to be due to the generation-recombination process in depletion region and limited by the minority carrier generation rate. The feasibility of integrating alternative gate dielectric on SiC by a low thermal budget process is demonstrated.

Enhancement of silicon oxidation rate due to tensile mechanical stress

Oxidation of silicon wafers under external mechanical stress was studied in this work. From the oxide thickness profile measured by an automatic ellipsometer, it was found that the oxidation kinetics of silicon was affected by the mechanical stress. The tensile stress strongly enhances the oxidation rate of silicon. A concept was proposed to explain this phenomenon by using a well-known physical Si–SiO2 lattice model. The tensile stress in the silicon will enlarge the atom spacing of silicon and make the oxidation to be easier and faster. A simulated deformation of silicon substrate under tensile stress was also given to support this concept. This work is a direct evidence of the effect of mechanical stress on silicon oxidation.

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.

An on-chip temperature sensor by utilizing a MOS tunneling diode

A simple metal-oxide-semiconductor (MOS) tunneling diode was demonstrated for application to an integrated temperature sensor. The MOS diode equipped with a 21-/spl Aring/ oxide was biased inversely at 1.8 V to monitor its substrate temperature through gate current. The gate current increased more than 700 times when the diode was heated from 20 to 110/spl deg/C. An exponential fitting curve correlated the gate current and the substrate temperature. Moreover, characteristics of the diode were analyzed though C-V and I/sub 1.8 V/-n/sub i/ curves. The good temperature response of the MOS tunneling diode might be useful in self-diagnosis or self-protection IC applications.

Thin-gate oxides prepared by pure water anodization followed by rapid thermal densification

Anodic oxidation at room temperature with pure deionized water as electrolyte and then followed by high-temperature rapid thermal densification was used to prepare high breakdown endurance thin-gate oxides with thicknesses of about 50 /spl Aring/. It was observed that the oxides prepared by anodic oxidation followed by rapid thermal densification (AOD) show better electrical characteristics than those grown by rapid thermal oxidation (RTO) only. The AOD oxides have a very low midgap interface trap density, Ditm, of smaller than 1/spl times/10/sup 10/ eV/sup -1/ cm/sup -2/ and negative effective oxide trapped charge. From the smaller leakage currents observed during staircase ramp voltage time-zero dielectric breakdown (TZDB) and constant field time-dependent dielectric breakdown (TDDB) testings, it is supposed that the uniform interfacial property and the pretrapped negative charges in AOD oxides are responsible for the improved characteristics.

High sensitive and wide detecting range MOS tunneling temperature sensors for on-chip temperature detection

This paper examined the feasibility of applying a highly sensitive metal-oxide-semiconductor (MOS) tunneling temperature sensor, which was compatible with current CMOS technology. As the sensor was biased positively at a constant voltage, the gate current increased more than 500 times when the sensor was heated from 20/spl deg/C to 110/spl deg/C. However, when the sensor was biased at a constant-current situation, its gate voltage magnitude changed significantly with substrate temperature, with a sensitivity exceeding -2 V//spl deg/C. The improvement of temperature sensitivity in this paper is one thousand times over the sensitivity of a conventional p-n junction, i.e., namely, about -2 mV//spl deg/C. Regarding a temperature sensor array, this paper proposes a method using gate current gain, rather than absolute gate current, to eliminate the gate current discrepancy among sensors. For constant current operation, a sensitivity exceeding 10 V//spl deg/C can be obtained if the current level is suitable. Finally, this paper demonstrates a real temperature distribution for on-chip detection. With such a high temperature-sensitive sensor, accurate temperature detection can be incorporated into common CMOS circuits.

Stress effect on the kinetics of silicon thermal oxidation

Oxidation of silicon wafers under external mechanical stress was studied in this work. From the oxide thickness profile measured by an automatic-scanning ellipsometer, it was found that the oxidation kinetics of silicon were significantly affected by mechanical stress. There are two distinct features of oxide thickness distribution corresponding to short and long times. By comparing the kinetic constants taken from experiments and the simulated stress distribution on the silicon wafer, we can possibly explain the two features of oxide thickness distribution: the initial rate constant is deformation dependent and the parabolic rate constant is stress dependent. The observed stress-dependent oxidation rates are important in the study of thin gate oxide reliability.

Comprehensive study on the deep depletion capacitance-voltage behavior for metal-oxide-semiconductor capacitor with ultrathin oxides

The deep depletion behaviors at the structure of Si/SiO2 with various equivalent oxide thicknesses (EOTs) are comprehensively studied by magnified capacitance versus gate voltage (C-V) curves of metal-oxide-semiconductor (P-substrate) capacitors in this work. According to the correlation between inversion tunneling current and deep depletion, it was found that the initiation voltage of deep depletion phenomenon increases with EOT (2.8–3.1 nm). After the constant voltage stress, the early occurrence of initiation voltage of deep depletion is observed after oxide breakdown. In addition, the uniform area ratio concept is proposed for the electrical characterization of deep depletion via local depletion capacitance model. It was novel for the evaluation of interfacial property between dielectric and Si substrate.

Clockwise C-V hysteresis phenomena of metal--tantalum-oxide--silicon-oxide--silicon ( p) capacitors due to leakage current through tantalum oxide

Thermal tantalum oxide with a thickness of 620 A was studied. The dc leakage resistance and high‐frequency (1‐MHz) resistance of a metal–tantalum‐oxide–silicon capacitor were found to be on the order of 108 and 1 Ω cm2, respectively. The C‐V behavior of the capacitor, with its initial states being carefully treated, was reproduced and observed to be dependent on the return voltage and hold time (at return point) of the measurement conditions. And only negative charges were observed to be responsible for the conduction current through tantalum oxide. A model with the considerations of the ac equivalent circuit and low‐frequency leakage characteristic of tantalum oxide was proposed for these observations. Theoretical examples, with their parameters being suitably given according to the measured data, were shown, and they explained the experimental observations quite well. It is found that the measurement conditions and effect of the ac resistance of tantalum oxide on the determination of flat‐band capacitan...