William Bishop

A heterogeneous environment for hardware/software cosimulation

A heterogeneous environment for hardware/software cosimulation is described. This environment permits a portion of an applications subsystems to be simulated using reconfigurable hardware while the remainder of the subsystems are simulated using software. An Aptix FPCB populated with Xilinx FPGAs serves as the hardware simulation platform while an IBM-compatible PC serves as the software simulation platform. The two platforms are connected using an Altera reconfigurable logic board which allows the development of a high-speed interface for communication. This paper focuses on the difficulties associated with designing and interfacing simulation entities in this heterogeneous environment. Strategies for designing hardware and software simulation entities are introduced. These strategies reduce the impact of size and performance constraints imposed by the cosimulation environment while addressing the issues of time management and synchronization. A simple queueing application is used to illustrate a design methodology which incorporates these design strategies.

Symmetric Multiprocessing on Programmable Chips Made Easy

Vendor-provided softcore processors often support advanced features such as caching that work well in uniprocessor or uncoupled multiprocessor architectures. However, it is a challenge to implement symmetric multiprocessor on a programmable chip (SMPoPC) systems using such processors. This paper presents an implementation of a tightly coupled, cache-coherent symmetric multiprocessing architecture using a vendor-provided softcore processor. Experimental results show that this implementation can be achieved without invasive changes to the vendor-provided softcore processor and without degradation of the performance of the memory system.

FPGA-Based Lossless Data Compression using Huffman and LZ77 Algorithms

Lossless data compression algorithms are widely used by data communication systems and data storage systems to reduce the amount of data transferred and stored. GZIP is a popular, patent-free compression program that delivers good compression ratios. This paper presents hardware implementations for the LZ77 encoders and Huffman encoders that form the basis for a full hardware implementation of a GZIP encoder. The designs have been implemented as state machines in VHDL in such a way that they are suitable for implementation using either FPGA or ASIC technologies. Performance metrics and resource utilization results obtained for a prototype implementation running on an Altera DE2 board are presented. Ultimately, the goal is to utilized the LZ77 encoders and Huffman encoders described in this paper to build a fully-functional, hardware design for a GZIP encoder that could be used in data communication systems and data storage systems to boost overall system performance.

Efficient least squares fusion of MRI and CT images using a phase congruency model

This paper presents an efficient and robust approach for MRI-CT image fusion using a phase congruency model. The fast fourier transform (FFT) is used to efficiently evaluate the similarity cost function. This approach is largely invariant to pixel intensity mappings.

Robust Invariant Descriptor for Symbol-Based Image Recognition and Retrieval

This paper presents a robust invariant descriptor for symbol-based image recognition and retrieval. A modified Hough-based Transform is used to extract parameter space information (i.e., position data and angular data) from a symbol image to derive an invariant descriptor. The proposed descriptor provides a compact representation of a symbol image that can be evaluated efficiently. The extracted descriptor is highly robust against geometric transformations such as translation, rotation, reflection, and scaling, and image degradation. A series of experiments were conducted using a set of architectural and engineering symbols subjected to geometric transformations and image degradation. The experimental results clearly show that the proposed descriptor can be used effectively for symbol recognition and retrieval.

Expert Knowledge Based Automatic Regions-of-Interest (ROI) Selection in Scanned Documents for Digital Image Encryption

Conventional image-oriented cryptographic techniques lack the flexibility needed for content-specific security features such as the concealment of confidential information within a portion of a document. Content-specific security is particularly important for digital archival systems that store sensitive documents in the form of digital images. Recently, a novel image encryption scheme utilizing multiple levels of regions-of-interest (ROI) privileges for digital document encryption was developed to address the needs of modern digital document management systems. This image encryption scheme requires the selection of regions-ofinterest for encryption. The process of manually selecting regions can be time-consuming. This paper presents an automatic, regions-of-interest selection algorithm that utilizes an expert knowledge learning system to select regions of interest in a scanned document image for the purpose of minimizing human interaction time during the encryption process. Experimental results show that a high level of accuracy and significant timesaving benefits can be achieved using the proposed algorithm.

A parameterizable SIMD stream processor

Stream processing is a data processing paradigm in which long sequences of homogeneous data records are passed through one or more computational kernels to produce sequences of processed output data. Applications that fit this model include polygon rendering (computer graphics), matrix multiplication (scientific computing), 2D convolution (media processing), and data encryption (security). Computers that exploit stream computations process data faster than conventional microcomputers because they utilize a memory system and an execution model that increases on-chip bandwidth and delivers high throughput. We have designed a general-purpose, parameterizable, SIMD stream processor that operates on IEEE single-precision floating point data. The system is implemented in VHDL, and consists of a configurable FPU, execution unit array, and memory interface. The FPU supports pipelined operations for multiplication, addition, division, and square root. The data width is configurable. The execution array operates in lock-step with an instruction controller, which issues 32-bit instructions to the execution array. To exploit stream parallelism, the number of execution units as well as the number of interleaved threads is specified as a parameter at compilation time. The memory system allows all execution units to access one element of data from memory in every clock cycle. All memory accesses also pass through a routing network to support conditional reads and writes of stream data. Functional and timing simulations have been performed using a variety of benchmark programs. The system has also been synthesized into an Altera FPGA to verify resource utilization

A Hardware Implementation of Real-Time Video Deblocking Using Shifted Thresholding

Video compression has become very important as demand has increased for the storage and transmission of digital video content. Popular video compression schemes like MPEG encoding make use of block-transform coding techniques which are susceptible to blocking artifacts. Recently, an efficient deblocking algorithm based on the concept of shifted thresholding has been proposed. This algorithm uses only integer arithmetic and replaces division operations with bit shifting. This paper proposes a new hardware architecture for the implementation of video deblocking using shifted thresholding. A prototype system for high performance video deblocking using a FPGA (field programmable gate array) board is described. The prototype system leverages the reduced hardware complexity of the shifted thresholding algorithm to cost-effectively implement video deblocking on a FPGA board.

kd-Tree traversal techniques

This article describes various kd-tree traversal techniques namely: omni-directional ray bundle traversal; cone traversal algorithm and multiple frustum traversal.

Practical Content-Adaptive Subsampling for Image and Video Compression

Subsampling is a commonly used technique for modern image and video compression. Existing image and video standards such as JPEG, MPEG, and H.264 provide support for uniform chroma subsampling. This paper presents an algorithm that uses adaptive luma subsampling based on a combination of three perceptually significant image characteristics (texture, edges, and brightness) to complement uniform chroma subsampling. The algorithm is computationally efficient, simple to implement, and easy to integrate into existing standards. Experimental results show that the introduction of adaptive luma Subsampling improves image quality both quantitatively and qualitatively when compared with the sole use of uniform chroma subsampling