Wayne M. Needham

High volume microprocessor test escapes, an analysis of defects our tests are missing

This paper explores defects found in a high volume microprocessor when shipping at a low defect level. A brief description of the manufacturing flow along with definition of DPM is covered. Three defective devices are then root cause analyzed for defect type, electrical effect and possible ways to screen earlier in the device life cycle or manufacturing process. The implications of these defects along with process trends are used to forecast the need for better tools and methods to earlier achieve high quality goals.

DFT strategy for Intel microprocessors

This paper describes the progress in DFT techniques applied to Intels X86-family microprocessors. The approach described here shows a progressive approach to increasing the level of DFT with increasing size and complexity of the design. Implementation of DFT is based on the needs of a given functional block and that of the overall chip. Test generation strategy to augment the coverage provided by DFT features is highlighted.

Just how real is the SIA roadmap

We debate the potential rocks listed in the Test section of The National Technology Roadmap for Semiconductors 1997. The 1997 Test Roadmap changed dramatically the numbers presented in the 1994 Test Roadmap. We can still question the speeds, currents, DFT and pins in the Roadmap. At the same time, we question is it real and what is our future? What we need to think of as challenges is not the lines in the roadmap, but the directions, walls and methods to get around those lines. In much the same way as testers evolved from shared resource to per pin architecture, we need to adapt to the needs of the roadmap. Either find ways to achieve the timing, power, and costs or someone else will do it for us. That someone could be circuit design, process design or a completely new test paradigm.