Wayne R. Burger

High performance silicon LDMOS technology for 2 GHz RF power amplifier applications

The structure, device processing and performance of a 2 GHz, 60 Watt silicon LDMOS RF power transistor are described. At 2 GHz with a 26 Vdc drain operating voltage this device has 1 dB power gain compression at 63 Watts CW and 44% drain efficiency. Under two-tone test conditions, at 60 Watts peak output, 11.2 dB power gain is realized with less than -30 dBc intermodulation distortion and greater than 30% drain efficiency. Excellent linearity is maintained over a wide dynamic range.

High efficiency LDMOS power FET for low voltage wireless communications

High efficiency, high gain power transistors are required to meet RF performance and output specifications as new generation portable communication products move towards lower voltage operations. A low cost, high efficiency silicon MOSFET using RFLDMOS (LV2) technology was developed in Motorola to operate at 3.4-12.5 V drain voltages. The LV2 device can deliver 70% power added efficiency with 12 dB gain, 31.5 dBm output power at 3.4 V and 850 MHz. This is the best known RF performance for silicon devices at 3.4 V. This paper focuses on 3.4 V LV2 device optimization and performance.

120 Watt, 2 GHz, Si LDMOS RF power transistor for PCS base station applications

The structure and performance of a 120 W, 2 GHz, Si RF LDMOS power transistor are described suitable for personal communication systems base station power amplifiers operating in the 1.8-2.2 GHz frequency band. The high gain (10.6 dB at 120 W CW, 2 GHz), and excellent linearity of this transistor, when operated in class-AB, (typically -30 dBc two-tone intermodulation distortion at 120 W PEP) makes it eminently suitable for amplification of digitally modulated signals.

RF-LDMOS: a device technology for high power RF infrastructure applications

RF-LDMOS is the dominant device technology used in high power wireless infrastructure applications for frequencies ranging from less than 900MHz to 2.7GHz. Its strong market leadership position is a direct result of the technologys delivery of superior performance (gain, efficiency, linearity) at low cost while remaining compatible with high supply voltages. This paper will review recent RF-LDMOS development at Freescale, focusing upon performance in the 2.1 GHz band. Opportunities for future device development will also be presented.

High efficiency 0.4 /spl mu/m gate LDMOS power FET for low voltage wireless communications

A low cost, high efficiency 4th generation silicon MOSFET using RFLDMOS (LV4) 0.4 /spl mu/m technology is presented which has been developed for high frequency (1-2 GHz) and low voltage (2.2-12.5 V) applications. Key results include 78% PAE at 31.8 dBm for 3.6 V, 900 MHz AMPS applications, and 63% PAE, 12.5 dB gain, 30.5 dBm for 2.4 V, 900 MHz for 2-way paging applications.

Intrinsic reliability of RF power LDMOS FETs

RF-LDMOS is the dominant RF power device technology in the cellular infrastructure market, having successfully displaced vertical MOSFETs and silicon bipolar transistors in the 1990s. A similar technology shift towards RF-LDMOS is occurring today in adjacent RF power markets such as UHF Broadcast, VHF Broadcast, L-Band and S-Band Radar, and the Industrial/Scientific/Medical markets (MRI, CO2 Laser, synchrotron, etc.). This increasing adoption of RF-LDMOS into these other RF power applications is the direct consequence of continuing progress at improving the intrinsic reliability and application-specific customization of LDMOS device structures. RF power applications, whether cellular infrastructure or the adjacent non-cellular markets, present unique and challenging thermal and electrical environments for the RF power transistor. While the design and architecture of the power amplifier is critically important in defining the stress environment, this presentation will focus on improvements of the intrinsic reliability of RF-LDMOS FETs. The most important of these intrinsic reliability characteristics are Hot Carrier Injection (HCI), Electromigration (EM), and device ruggedness. The stress environment presented to the RF power transistor will be described in detail, including the linkage between the RF stress and these intrinsic reliability metrics. Detailed models have been created to simulate these stresses, and the results of various device design strategies to mitigate these stresses will be presented.

High efficiency submicron gate LDMOS power FET for low voltage wireless communications

A low cost, high efficiency silicon MOSFET using 0.6 /spl mu/m LDMOS (LV3) technology was developed in Motorola for high frequency (1-2 GHz) and low voltage (3.4-12.5 V) wireless applications. The LV3 devices can deliver 77% power added efficiency (PAE) with 12 dB gain, 28.7 dBm output power at 3.4 V and 850 MHz. The LV3 devices also can provide 70% PAE, 11 dB gain, 36 dBm Pout at 6 V, 850 MHz and 50% PAE, 9 dB gain, 33 dBm Pout at 5.8 V, 1.9 GHz. This is the best known RF performance for silicon devices at 3.4 V and 6 V.

Analysis of distributed multi-finger high-power transistors using the FDTD method

The FDTD method has been used for the EM analysis of the power scaling versus gate periphery in distributed multi-finger, large area RF power transistors, such as RF LDMOS, the dominant technology in cellular base-station applications. Results show that, regardless of transistor optimization for better RF performance, there is a strong degradation of the RF power density when scaling multi-finger dies to large size, due solely to EM effects. Therefore, EM effects within the active region of the transistor should be thoroughly accounted for in the design process of transistors for ultra high power amplifiers.