Weera Pengchan

Electrical Characteristics of Different Gate Geometry of FinFET

This paper proposed to the electrical characteristics of difference gate geometry of FinFET. Four of difference gate structure have been designed and simulated by GTS Framework TCAD software which is simulation the characteristics of FinFET device include drain current-voltage, threshold voltage and subthreshold swing. Then, the electrical characteristics was compared. From the result found that the drain current depend on gate geometry of FinFET. The largest gate geometry of FinFET device was the rectangle shape with gate width at 66 nm, IDS about 19.8 mA and VTH = 0.5 V and the smallest gate geometry, the triangle shape with gate width at 52 nm and give IDS about 8.5 mA and Vth = 0.5 V.

Effect of Temperature on 16 nm n-FiNFET

This research presents the effect of temperature that influence to the performance of 16 nm SOI n-FinFET structure. The structure has created with structure tool on GTS Framework. The transistor has 1 nanometer HfO2 gate oxide with all metal contact and biased on Minimos-NT tool, with variation of temperatures from 300 K to 420 K with 30 K per step. The result found the decrease in saturation current, threshold voltage and mobility. The temperature brought electron and rose the density of electron as the potential from power supply that energized to the structure. They made mobility fall with them rising. The temperature makes a performance of FinFET structure.

Yield Analysis Based on the Defect Analysis with Derivative Method

This paper presented the corresponding between the yield equation prediction from Poisson, Murphy with wafer actual yield on the silicon wafer with 0.8 μm CMOS technology. The defect analysis with derivative method, current - voltage and capacitance-voltage of diode characteristic measurement, is used to define the defect in p-n junction on silicon wafer. The different sampling numbers of chips are used to calculate the yield. Finally the calculated data and actual would be compared and found that at sampling number is 25, the tolerance from actual yield is less than 3%.

Defect Distribution and Yield Analysis Technique on Silicon Wafer

This paper presents the defect distribution and yield analysis on silicon wafer. The generation and recombination lifetime were the key parameters and obtained from the currentvoltage and the capacitancevoltage of diode characteristics for forward bias. Then 3D contour maps were plotted as defect distribution and can be analyzed for the whole wafer which is useful for the yield analysis of the defects that were caused from fabrication process.

Power Loss Analysis Based on Leakage Currentin PN Junctions

This paper is proposed to analyze the power loss from leakage current in p-n junctions in case of non-uniform defects. The different geometry p-n junctions have been fabricated by a standard 0.8 micron CMOS technology. The diode fabricated by the ion implantation process with two different condition. The reverse current and voltage (I-V)characteristics at varied temperature of p-n junctions have been measured. The power loss coefficient can be extracted from the leakage current versus temperature. Form the derivative of leakage current with temperature, the power loss with prediction trend curve can be obtained.

The defects analysis in CMOS fabrication by arrhenius activation energy technique

Low power consumption device can be realized by low junction leakage current. This leakage current relates to the defects in the depletion region of p-n junction. Among variety process steps, implantation step may generate defects. Therefore, the implantation-induced defects have been studied from the activation energy which has been obtained from the leakage current of p-n junction. The different geometry p-n junctions have been fabricated by a standard CMOS technology. The current-voltage (I–V) and high frequency capacitance-voltage (C-V) characteristics of p-n junctions with temperature dependence have been measured. The electrically active defects from implantation process can be extracted from the junction generation current density versus temperature. Base on this analysis, it will be demonstrated that the implantation-induced defects have been found in p+-n-well more than in n+-p-substrate. Finally, the possible nature of the defect will be discussed.

Improved Extraction of the Local Carrier Generation Lifetime from Forward Diode Characteristics

This paper is proposed to extract the local carrier generation lifetime from forward current-voltage (I-V) characteristics of p-n junctions in case of non-uniform defects. The different geometry p-n junctions have been fabricated by a standard CMOS technology. The forward I-V and high frequency capacitance-voltage (C-V) characteristics of p-n junctions have been measured. The recombination current density can be extracted from the area forward current density by subtracting with the area diffusion current density. Form the recombination current density, the local generation and recombination lifetime can be obtained.

Extraction of Defect in Doping Silicon Wafer by Analyzing the Lifetime Profile Method

The total leakage current in silicon p-n junction diodes compatible with 0.8 µm CMOS technology is investigated. The generation lifetime is a key parameter for the leakage current, which can be obtained from the current-voltage (I-V) and the capacitance-voltage (C-V) characteristics. As will be shown, the electrically active defect from ion implantation process generated in p-n junction can be extracted from the generation current density.

Effect of Base Width and Implantation Dose on Performance of 3-Terminal Magnetotransistor

This paper presents the effect of base width and implantation dose on electrical carriers in the magnetotransistor deflected by the Lorentz force (FL) from magnetic field. The structure of magnetotransistor is designed like a structure of a PNP bipolar junction transistor which comprises of 3 terminals, i.e., emitter, collector and base. The base width (L) is varied (10, 20 and 30 mum) where the spacing between collector and base is fixed at 40 mum. The emitter and collector regions are doped with boron (BF2) at the dose of 3times1015, 5times1015 and 1times1016 ions/cm2. It is found that the sensitivity is increased when increasing L and the implantation dose. It is also demonstrated that the linear relationship between the output voltage of the magnetotransistor circuit and magnetic field can be obtained.