Wei Baolin

Low-noise sub-harmonic injection locked multiloop ring oscillator*

A three-stage differential voltage-controlled ring oscillator is presented for wide-tuning and low-phase noise requirement of clock and data recovery circuit in ultra wideband (UWB) wireless body area network. To improve the performance of phase noise of delay cell with coarse and fine frequency tuning, injection locked technology together with pseudo differential architecture are adopted. In addition, a multiloop is employed for frequency boosting. Two RVCOs, the standard RVCO without the IL block and the proposed IL RVCO, were fabricated in SMIC 0.18 μ m 1P6M Salicide CMOS process. The proposed IL RVCO exhibits a measured phase noise of -112.37 dBc/Hz at 1 MHz offset from the center frequency of 1 GHz, while dissipating a current of 8 mA excluding the buffer from a 1.8-V supply voltage. It shows a 16.07 dB phase noise improvement at 1 MHz offset compared to the standard topology.

Demonstration of a fully differential VGA chip with small THD for ECG acquisition system

We present both a theoretical and experimental demonstration of a fully differential variable gain amplifier (VGA) with small total harmonic distortion (THD) for an electrocardiogram (ECG) acquisition system. Capacitive feedback technology is adopted to reduce the nonlinearity of VGA. The fully differential VGA has been fabricated in SMIC 0.18-μm CMOS process, and it only occupies 0.11 mm2. The measurements are in good agreement with simulation results. Experimental results show that the gain of VGA changes from 6.17 to 43.75 dB with a gain step of 3 dB. The high-pass corner frequency and low-pass corner frequency are around 0.22 Hz and 7.9 kHz, respectively. For each gain configuration, a maximal THD of 0.13% is obtained. The fully differential VGA has a low THD and its key performance parameters are well satisfied with the demands of ECG acquisition system application in the UWB wireless body area network.

An extremely low power voltage reference with high PSRR for power-aware ASICs

An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18-μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/°C in a range from 25 to 100 °C. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3.3 V, and PSRR is −49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs.