Wei Xueming

Low-noise sub-harmonic injection locked multiloop ring oscillator*

A three-stage differential voltage-controlled ring oscillator is presented for wide-tuning and low-phase noise requirement of clock and data recovery circuit in ultra wideband (UWB) wireless body area network. To improve the performance of phase noise of delay cell with coarse and fine frequency tuning, injection locked technology together with pseudo differential architecture are adopted. In addition, a multiloop is employed for frequency boosting. Two RVCOs, the standard RVCO without the IL block and the proposed IL RVCO, were fabricated in SMIC 0.18 μ m 1P6M Salicide CMOS process. The proposed IL RVCO exhibits a measured phase noise of -112.37 dBc/Hz at 1 MHz offset from the center frequency of 1 GHz, while dissipating a current of 8 mA excluding the buffer from a 1.8-V supply voltage. It shows a 16.07 dB phase noise improvement at 1 MHz offset compared to the standard topology.

Demonstration of a fully differential VGA chip with small THD for ECG acquisition system

We present both a theoretical and experimental demonstration of a fully differential variable gain amplifier (VGA) with small total harmonic distortion (THD) for an electrocardiogram (ECG) acquisition system. Capacitive feedback technology is adopted to reduce the nonlinearity of VGA. The fully differential VGA has been fabricated in SMIC 0.18-μm CMOS process, and it only occupies 0.11 mm2. The measurements are in good agreement with simulation results. Experimental results show that the gain of VGA changes from 6.17 to 43.75 dB with a gain step of 3 dB. The high-pass corner frequency and low-pass corner frequency are around 0.22 Hz and 7.9 kHz, respectively. For each gain configuration, a maximal THD of 0.13% is obtained. The fully differential VGA has a low THD and its key performance parameters are well satisfied with the demands of ECG acquisition system application in the UWB wireless body area network.

Improving Breakdown Behavior by Substrate Bias in a Novel Double Epi-layer Lateral Double Diffused MOS Transistor

A new lateral double diffused MOS (LDMOS) transistor with a double epitaxial layer formed by an n-type substrate and a p-type epitaxial layer is reported (DEL LDMOS). The mechanism of the improved breakdown characteristic is that the high electric field around the drain is reduced by substrate reverse bias, which causes the redistribution of the bulk electric field in the drift region, and the vertical blocking voltage is shared by the drain side and the source side. The numerical results indicate that the trade-off between breakdown voltage and on-resistance of the proposed device is improved greatly in comparison to that of the conventional LDMOS.

Substrate-bias effect on the breakdown characteristic in a new silicon high-voltage device structure

A novel silicon double-RESURF LDMOS structure with an improved breakdown characteristic by sub- strate bias technology (SB) is reported. The P-type epitaxial layer is embedded between an N-type drift region and an N-type substrate to block the conduction path in the off-state and change the distributions of the bulk electric field. The substrate bias strengthens the charge share effect of the drift region near the source, and the vertical elec- tric field peak under the drain is decreased, which is especially helpful in improving the vertical breakdown voltage in a lateral power device with a thin drift region. The numerical results by MEDICI indicate that the breakdown voltage of the proposed device is increased by 97% compared with a conventional LDMOS, while maintaining a low on-resistance.