Wei-Hao Chen

Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things

For the first time, a CO2 far-infrared laser annealing (CO2-FIR-LA) technology was developed as the activation solution to enable highly heterogeneous integration without causing device degradation for TSV-free monolithic 3DIC. This process is capable to implement small-area-small-load vertical connectors, gate-first high-k/metal gate MOSFETs and non-Al metal inter-connects. Such a far-infrared laser annealing exhibits excellent selective activation capability that enables performance-enhanced stacked sub-40nm UTB-MOSFETs (Ion-enhanced over 50 %). Unlike TSV-based 3D-IC, this 3D Monolithic IC enables ultra-wide-IO connections between layers to achieve high bandwidth with less power consumption. A test chip with logic circuits, 6T SRAM, ReRAM, sense amplifiers, analog amplifiers and gas sensors was integrated to confirm the superiority in heterogeneous integration of proposed CO2-FIR-LA technology. This chip demonstrates the most variable functions above reported 3D Monolithic ICs. This CO2-FIR-LA based TSV-free 3D Monolithic IC can realize low cost, small footprint, and highly heterogeneous integration for Internet of Things.

Dilute manganese-doped ZnO nanowires for high photoelectrical performance

This study developed dilute manganese-doped ZnO (D-(Zn,Mn)O) nanowires using a low temperature hydrothermal method. The material properties of the resulting nanowires were examined using field emission scanning electron microscopy (FESEM), X-ray diffraction (XRD), and high-resolution transmission electron microscopy (HRTEM). We investigated the optoelectronic properties and energy band transformation of ZnO nanowires doped with various concentrations of Mn according to the photoluminescence (PL) spectrum, Raman spectra, X-ray absorption near edge structure (XANES), and absorption spectrum. UV sensors with individual D-(Zn,Mn)O nanowires were then fabricated using a focus ion beam (FIB) system. The resulting sensor demonstrated outstanding photoelectric performance with faster response speed and short recovery time than those of devices using pure ZnO nanowires. The efficacy of the sensors was evaluated according to the light on–off ratio (ΔI = Ilight/Idark). We also proposed a possible mechanism for the UV response of the proposed D-(Zn,Mn)O nanowires and investigated the possibility of using numerical simulation to predict the characteristics of D-(Zn,Mn)O nanowires, via a novel application of density function theory.

A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory

An energy-efficient nonvolatile intelligent processor (NIP) is proposed for battery-less energy harvesting system. This NIP employs RRAM-based nonvolatile logics (NVL) with self-write-termination (SWT) scheme and low-power processing-in-memory (PIM) to achieve energy-efficient computing against frequent power-off situations. An NIP test chip was fabricated in 150nm CMOS process using HfO RRAM. This NIP chip achieves 462GOPs/J energy efficiency at 20MHz clock frequency, showing 13× performance improvement over state-of-the-arts. This work presents the first nonvolatile processor capable of general as well as neural network computing in addition to the first integrated chip using RRAM-based PIM.

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support

We present a novel 3D-SRAM cell using a Monolithic 3D integration (M3D-IC) technology for realizing both robustness and In-memory Boolean logic compute support. The proposed two-layer design makes use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, XNOR/XOR) without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes and evaluate the energy efficiency of our proposed design. Assist techniques improve SRAM read stability by 2.2x and increase the write margin by 17.6%, while staying within the SRAM footprint. By virtue of increased robustness, the cell enables seamless operation at lower supply voltages and thereby ensures energy efficiency. Energy Delay Product (EDP) reduces by 1.6x over standard 6T SRAM with a faster data access. Transistor placement and their biasing technique in layer-2 enables In-memory bitwise Boolean computation. When computing bulk In-memory operations, 6.5x energy savings is achieved as compared to computing outside the memory system.

Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing

Emerging memory devices enable performance improvements in memory applications and make possible chip designs using beyond von Neumann architectures. This paper explores the use of emerging memory devices in applications of nonvolatile logics and neuromorphic computing, and provides a review of several silicon examples of nonvolatile logics. This paper also discusses the challenges involved in the design of circuits for nonvolatile logics and neuromorphic computing systems based on emerging memory devices.

Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via

This paper proposes to use the high density of vias enabled by monolithic 3D integration to produce multi-stack FPGA designs with improved performance and functionality. The use of fine grain vertical interconnects enables reconfiguration of FPGA logic within a few clock cycles, as shown in our design that features dynamic reconfiguration capabilities through the use of a pair of configuration memories on the upper stack. Along with the reconfigurability feature, results show that our SLICE design offers an area reduction of 23% compared to a standard design without reconfiguration capability. Our analysis of FPGA switch box logic and physical design with M3D vias provides insights into the sources of benefits from vertical routing in a multi-stacked design. We also discuss the design overheads involved in incorporating multiple inter-stack vias for better and faster communication among logic routed in different design stacks.