Wei-Hao Chiu

A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops

This paper presents a fast-locking technique for phase-locked loops (PLLs). In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process. The detected phase error is then coarsely compensated by dynamically changing the divide ratio of the frequency divider. The proposed method allows the PLL to maintain a small phase error throughout the frequency acquisition process, thereby reducing the settling time. To further enhance the locking speed, an auxiliary charge pump is employed to supply currents to the loop filter during the fast-locking mode to facilitate a rapid frequency acquisition. The proposed technique is incorporated in the design of a 5-GHz PLL. Fabricated in the TSMC 0.18-μm CMOS technology, the whole PLL dissipates 11 mA from a 1.8-V supply. The measured settling time is considerably improved over previous bandwidth-switching method. At 5.34 GHz, the phase noise measured at 1-MHz offset is -114.3 dBc/Hz, and the reference spurs at 10-MHz offset are lower than -70 dBc.

A Synchronous 50% Duty-Cycle Clock Generator in 0.35-

This paper presents a synchronous 50% duty-cycle clock generator (DCCG). The proposed DCCG circuit comprises of a clock generator and a phase error integrator. The clock generator is edge-triggered by an input signal to produce an output whose pulse width is determined by a delay line. The delay line is controlled by the phase error integrator which detects the phase difference between the input and output signals. The proposed DCCG is designed such that when the phase error is zeroed, i.e., the input and output signals are synchronized, the delay is properly adjusted and the output signal duty cycle converges to 50%. The proposed DCCG is implemented in a 0.35-μm CMOS process. The circuit can operate from 70 to 500 MHz, and accommodates a wide range of input duty cycle ranging from 5% to 95%. The duty-cycle error of the output signal is less than 1.5%. Operated from a 3.3-V supply voltage, this circuit dissipates 7 mA at 500 MHz.

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This work presents a phase-locked loop (PLL) with a fast-locking capability. The PLL incorporates a proposed digital discriminator aided phase detector (DAPD) to expedite the loop settling. The DAPD enables a fast locking by sensing the input phase error to adjust the programmable charge pump and loop filter. Moreover, two digital frequency dividers, one divide-by-2 and one divide-by-4/5, are proposed to accomplish low-power and high-speed divider operation. The PLL is fabricated in a 0.18-mum CMOS process. With the proposed digital DAPD, the settling time is considerably reduced to 20 mus without sacrificing the characteristics of a 40-kHz loop bandwidth at lock. The measured 5.5-GHz PLL phase noise at 1-MHz offset is -110.8 dBc/Hz, and the reference spurs at 10-MHz. offset are lower than -75 dBc. The whole PLL consumes 9 mA from a 1.8-V supply voltage, while the two high-frequency dividers consume 1.4 mA only.

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A multi-band FSK transmitter (Tx) is presented in this paper. The Tx is designed to operate at the ISM frequency bands at 433/868/915 MHz, 2.4 GHz, and MICS band at 402~405 MHz, and supports a data rate well over 1 Mbps. The Tx adopts an analog modulator which allows a deviation frequency ranging from 714 kHz to 3.2 MHz. In addition, this work proposes an inductor-less wideband mixer and a voltage-controlled oscillator to save the chip area. Fabricated in a 0.18-μm CMOS process, the proposed Tx consumes 8.9 mA to 12 mA from a 1.8-V supply voltage at different frequency bands. The measured FSK errors range from 13.9 % to 15.4 %, which are adequate for most low-cost wireless applications. The proposed multi-band Tx occupies an area of 1.6 mm × 1.9 mm.

A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS

A 3rd-order 1-bit continuous-time delta-sigma modulator (CTDSM) is reported. By shaping the 1-bit DAC feedback current with the proposed multi-step return-to-zero (RZ) waveform, the CTDSM achieves reduced sensitivity to clock jitter. In addition, the modulator adopts a proposed excess-loop-delay (ELD) compensation scheme. For a 4-MHz bandwidth, the CTDSM achieves a dynamic range of 71.5dB and a peak SNDR of 69 dB. Fabricated in a 0.18-μm CMOS, this chip dissipates 16.9 mW from a 1.8-V supply.

A 400-MHz/900-MHz/2.4-GHz multi-band FSK transmitter in 0.18-μm CMOS

A wideband active-RC low-pass filter realized for high data rate wireless receivers is reported in this paper. This filter adopts the 5th-order elliptic topology and achieves a bandwidth of 120 MHz and a stopband attenuation of more than 45 dB. The wide-bandwidth operational amplifiers employed in the filter adopt the feedforward compensation technique to extend the unity-gain bandwidth to 4.1 GHz. An agile tuning scheme is also proposed to automatically adjust the filter cutoff frequency. It uses the successive approximation register counter in the digital tuning loop to compensate for the RC variations while achieves short calibration time. The filter is fabricated in the TSMC 0.18-mum CMOS process and dissipates 38 mW under 1.5-V supply voltage. The measured IIP3 is 21 dBm and the tuning time is 8 mus.

A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter

This work proposes a fractional phase error compensation approach for a classical fractional-N phase-locked loop (PLL) to reduce fractional spurs. The proposed corresponding-phase compensation technique incorporates a divider array and an auxiliary charge pump pair to overcome the fractional phase error. The main advantage of the proposed fractional-N PLL is that it only uses a constant compensation ratio when being a desired divide ratio. This PLL is fabricated in the TSMC 0.13μm CMOS process. The total power consumption is about 17 mW. The measured results show that, with the proposed corresponding-phase compensation technique, the fractional spurs are reduced under classical fractional-N PLL.

A 120-MHz active-RC filter with an agile frequency tuning scheme in 0.18-μm CMOS

This work presents a charge pump (CP) calibration technique for a Delta-Sigma fractional-N phase-locked loop (ΣΔ-FNPLL). The proposed calibration method introduces an auxiliary path to the CP circuit and utilizes some interval within each reference cycle to detect the mismatch and then correct the up/down current difference. The proposed CP calibration is employed in the design of a 2.4-GHz ΣΔ-FNPLL. The experimental result has demonstrated that the in-band phase noise and fractional spurs are significantly reduced when the proposed CP calibration is activated. Fabricated in a TSMC 0.18-μm CMOS process, the whole ΣΔ-FNPLL consumes 23 mW from a 1.8-V supply.