Wei-Lun Wang

An on-chip march pattern generator for testing embedded memory cores

In this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data within the steps of the algorithms. Therefore, the proposed pattern generator is capable of generating any march algorithm with small area overhead.

A complete memory address generator for scan based March algorithms

The March algorithm based built-in self-test (BIST) schemes have been widely used to test memory chips (cores). Conventional methods which use binary counters to generate the addresses may require large routing area when the addresses are to be broadcast to multiple memory cores. In this paper we propose to use linear feedback shift registers (LFSRs) to generate the memory addresses which can be serially applied to the memory cores under test and thus the routing area overhead can be greatly reduced. We have designed a complete up/down LFSR which can generate complete March addresses, including all 2/sup n/ up and 2/sup n/ down sequences. Also theoretic analysis has been done which guarantees the transitions from up to down and down to up sequences can all be smoothly carried out such that the memory under test can receive a different address per clock cycle even during the transitions.

An embedded march algorithm test pattern generator for memory testing

The memory cores are essential for a system-on-a-chip (SOC). To test the memory cores, in this paper we propose a generalized embedded test pattern generator for any march algorithm. Without loss of functionality of the march algorithm, we also present a systematic procedure with a short time complexity to reduce the hardware cost of the test pattern generator.

A universal march pattern generator for testing embedded memory cores

In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.

An automatic design for flash memory testing

Due to the easy implementation and high fault coverage, the march-like algorithms have been used for the flash memory testing. However, the testing complexity of the flash memory testing is mainly dominated by the memory address spaces. Many tremendous human efforts are required to design a built-in self-test test pattern generator for a large capacity of flash memory. To save the design overhead, an automatic design for any size of flash memory testing has been proposed in this paper. By using the Microsoft Visual Basic (VB) programming tool, a graphical user interface (GUI) has been designed for the user to apply the specification of flash memory. Then the test pattern generator of the embedded march-like algorithms for testing the flash memory has been designed automatically and converted to the hardware description language (HDL) file. Under the control of the VB, without any manual labor, the HDL file can be compiled and simulated by the Altera FPGA tool - Quartus II and converted to the specific files for applying the Data Generator Instruments to generate the test signals.

An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.

A fast testing method for sequential circuits at the state transition level

In this paper an efficient method called the fast augmented state transition (FAST) test method is proposed to alleviate the testing problem of sequential circuits at the state transition level. By adding some extra logic gates to a sequential circuit under test the FAST method guarantees that each state of the augmented circuit has both the shortest distinguishing and synchronizing sequences, hence the testing complexity can be greatly reduced. The test length of the FAST method is shorter than any other exhaustive testing approaches based on the state transition level. Furthermore the test set for the augmented circuit can be easily identified.

A new pseudo-exhaustive test method

An efficient and systematic pseudo-exhaustive test pattern generation algorithm has been proposed in this paper to solve the problem of test generation in BIST. The algorithm has the following advantages: (1) it requires a minimum number of test signals for testing a circuit (2) it executes quickly with polynomial time complexity (3) it requires fewer test patterns and low hardware cost compared to five previous proposed methods.<<ETX>>