Kuen-Jong Lee

Peak-power reduction for multiple-scan circuits during test application

This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is proposed which can significantly reduce the peak power. This method can be efficiently employed in a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. The improvement percentage can be up to 50% when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, 76% of peak-power reduction can be achieved.

A practical current sensing technique for I/sub DDQ/ testing

In this paper, a practical design for built-in current sensors (BICSs) is proposed. This scheme can execute current testing during the normal circuit operation with very small impact on the performance of the circuit under test (CUT). In addition, scalable resolutions and no external voltage/current reference make this design more effective and efficient than previous designs. Moreover this scheme can be used to monitor the current-related faults of both CMOS and non-CMOS circuits. Thus it is highly suitable for design for testability (DFT) on a multiple-chip module (MCM) or to be the current monitor on the test fixture under the quality test action group (QTAG) standard. >

Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults

All possible bridging faults (BFs) between any two circuit nodes are considered, where a circuit node may be the drain, source, or gate terminal of a transistor. Several examples are given to show that under certain circumstances current supply monitoring (CSM) cannot give correct test results. A circuit partitioning model is described, and a minimal set of design and test rules is presented. This set of rules is minimal in the sense that if any one of these rules is removed, then circuits exist for which CSM cannot give correct test results. When all the rules are satisfied it can be formally shown that: (1) all signal irredundant BFs can be detected by single vector tests, and (2) a test vector that detects a single bridging fault f/sub 1/ also detects all multiple BFs that contain f/sub 1/. To enhance the applicability of CSM, test and/or design strategies for dealing with circuits that do not satisfy each rule are proposed. Such circuits include a special exclusive OR gate, BiCMOS circuits, domino logic, synchronous sequential circuits, and circuits implemented by the silicon on insulator (SOI) technology. >

Reduction of power consumption in scan-based circuits during test application by an input control technique

This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application time. The basic idea is to identify an input control pattern (CP) for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be reduced or even eliminated. A D-algorithm-like CP generator is developed to generate the CP. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve 22.37% of average improvement by redoing the experiments in previous work using our test sets, while 34.23% average improvement can be achieved if the input control technique is employed after the latch ordering and vector ordering techniques.

An on chip ADC test structure

In this paper; a new built-in self-test structure to test the static specifications of analog to digital converters (ADCs) is presented. A ramp signal generated by an integrator serves as a test input signal. A specific range of this signal is divided into 2/sup n+1/ segments, with each segment corresponding to one output combination of an n+1-bit counter; where n is the number of bits of the ADCs under test. The testing process is done with digital data processing by comparing the outputs of ADCs under test with the outputs of the n+1 bit counter. Simple structure, low area overhead, and high speed are the advantages of the proposed test structure.

A token scan architecture for low power testing

Presents a novel scan architecture for low-power testing, which employs the techniques of multiphase clocking, token ring, and clock-gating. When the multiphase clocking technique is directly employed to a scan chain, inter-phase skews and large routing area will be the problems. We develop a token scan cell design to address these problems. To reduce the power dissipation due to the clock and scan-in data trees, we propose a novel clock-gating technique that takes advantage of the regularity and periodicity of the token scan chain. Combining the three techniques, the token scan architecture can efficiently reduce the data transitions in the scan circuits as well as the switching activity in both the clock and the scan-in data trees. From experiments, more than 95% of power reduction can be achieved for most circuits with long scan chains.

A novel test methodology based on error-rate to support error-tolerance

As the advance of VLSI technology approaches physical limitations, the yield associated with high performance system-on-chip (SOC) designs continue to decline. Conventional methodologies to address this problem, such as fault-tolerance and defect-tolerance, may become inadequate. Recently, the concept of error-tolerance has drawn much attention. Under this new concept, some defective chips (or systems) can still be labeled as acceptable, i.e., marketable, even if some outputted results are erroneous. The motivation for employing error-tolerance is to significantly increase the effective yield of some chips when used in certain applications. In this paper, we propose a novel error-rate based test methodology to support the notion of error-tolerance. Several definitions, such as various measures of yields, individual-fault and system error-rates, defect level and unacceptable defect levels are clarified or redefined. Analytically derived measures are formulated to estimate the error-rate associated with a fault, and to generate lists of faults that are acceptable with respect to a specified upper bound on the system error-rate. These results include consideration of the degree of confidence of an estimate, and provide a theoretic basis that enables the practical application of the concept of error-tolerance to both test set reduction and yield improvement. Experimental results show that the proposed test methodology can easily identify a set of acceptable faults, i.e., faults that might occur but need not cause the part to be discarded. The increase in effective yield depends on requirements imposed by end users. We show that a significant improvement in effective yield can be achieved for some applications

A current-mode testable design of operational transconductance amplifier-capacitor filters

Analog filters are important building blocks of many communication and instrumentation systems. However, similar to other analog circuits, testing an analog filter is a difficult problem. In recent years, this problem has become even more difficult because of the increase of circuit complexity. Operational transconductance amplifier-capacitor (OTA-C) filters are especially useful in video applications such as HDTV. In this paper, we first present the design of an OTA-C low-pass filter with a passband from 0 to 4.5 MHz. We then propose a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently detected. This technique has been applied to the OTA-C filter and a testable design is obtained. Experimental results show that our design has the following advantages: (1) easy to design and implement; (2) high accuracy in error detection; (3) little impact on the circuit performance of the filter; and (4) high error-detection speed. From an actual layout, we find that the area overhead is about 25% and only one extra pin is needed.

Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores

This paper presents an effective hybrid test program for the software-based self-testing (SBST) of pipeline processor cores. The test program combines a deterministically developed program which explores different levels of processor core information and a block-based random program which consists of a combination of in-order instructions, random-order instructions, return instructions, as well as instruction sequences used to trigger exception/interrupt requests. Due to the complementary nature of this hybrid test program, it can achieve processor fault coverage that is comparable to the performance of the conventional scan chain method. The test response observation methods and their impacts on fault coverage are also investigated. We present the concept of micro observation versus macro observation and show that the most effective method of using SBST is through a multiple input signature register connected to the processor local bus, while conventional methods that observe only the program results in the memory lead to significantly less processor fault coverage.

An embedded processor based SOC test platform

In this paper, we present a novel test platform for embedded processor based system-on-a-chip (SoC). The embedded processor is employed as a control kernel to execute the test programs for all the cores in the SoC. A dedicated test access mechanism (TAM) controller is developed which controls the actual test procedure for each core such that no extra buffer is needed for individual cores. The TAM controller together with the test programs can execute scan-based testing, memory BIST and mixed-signal BIST. The platform can test cores wrapped by the standard boundary scan and the IEEE P1500 wrappers, as well as hierarchical and mixed-signal cores. Our methodology alleviates the need of expensive automatic test equipment (ATE), and hence can greatly reduce the total test cost. Experimental results show the effectiveness of the proposed test platform.