Wei-Min Chao

A novel hybrid motion estimator supporting diamond search and fast full search

We present a novel hardware architecture supporting diamond search and fast full search for block matching motion estimation. It can handle irregular data flow of these fast algorithms without pipeline bubbles, and reduce computation of duplicated search positions. The proposed architecture needs preprocessing with a small amount of computational power while performing fast full search and is suitable for the platform-based video coding system. While the diamond search mode can be applied for real-time requirements, we can choose the fast full search mode, which adapts the processing cycles to picture contents and preserves the same quality of full search block matching (FSBM), for applications of high picture quality or compression ratio. It needs only 9K gates and one additional memory of search range size and is more cost-effective than the conventional systolic array architecture.

A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications

A 5mW MPEG4 SP encoder is implemented on a 7.7mm2 die in 0.18mum CMOS technology. It encodes CIF 30frames/s in real-time at 9.5MHz using 5mW at 1.3V and VGA 30frames/s at 28.5MHz uses 18mW at 1.4V. This chip employs a 2D bandwidth-sharing ME design, content-aware DCT/IDCT, and clock gating techniques to minimize power consumption

Architecture design of full HD JPEG XR encoder for digital photography applications

To satisfy the high quality image compression requirement, the new JPEG XR compression standard is introduced. The analysis and architecture design with VLSI architecture of JPEG XR encoder are proposed in this paper which can encode 4:4:4 1920 times 1080 high definition photo in smooth. According to the simulation results, the throughput of the proposed design can encode 44.2 M samples/sec. This design can be used for digital photography applications to achieve low computation, low storage, and high dynamical range features.

Pyramid Architecture for 3840 X 2160 Quad Full High Definition 30 Frames/s Video Acquisition

Image pipeline processing is crucial to generating high quality images in applications using complementary metaloxide-semiconductor (CMOS)/charge-coupled device sensors. The on-chip line buffer normally dominates the total area and power dissipation due to the needed filter window buffering. As image resolution and filter support increase, the area and power requirement increase accordingly. This paper presents a novel pyramid architecture to efficiently process a system that the image pipeline is between an image sensor and video coding engine. By utilizing the features of the pyramid structure and block-based video/image encoders, the proposed architecture is scalable from low to high image resolution and filter size. The input image is first partitioned into floors of tiles to reduce the frame line buffer. Two computing schemes, immediate result reuse and vertical snack scan, are utilized to reduce the overlapping redundant computations. A 90 nm CMOS chip design with 7 × 5 filter support for 3840 × 2160 quad full high definition video at 30 frames/s is designed to demonstrate the performance of power and area efficiency. Compared with traditional architectures with frame line buffers, the proposed design has shown that the power consumption is reduced by 25% to 108 mW from 145 mW. The chip area is reduced by 65% to 309 K from 888 K logic gates. The external memory bandwidth increases to 8286 Mbit/s from 5972 Mbit/s for YUV4:2:0, from 7963 Mbit/s for YUV4:2:2, and is reduced by 30% from 11944 Mbit/s for YUV4:4:4.

An efficient embedded bitstream parsing processor for MPEG-4 video decoding system

In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.

Platform-based MPEG-4 video encoder SOC design

An MPEG-4 video coding SOC design is presented. We adopt a platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented to provide a compromise between compression performance and design cost. The proposed data reuse scheme reduces the required memory access bandwidth. Several key modules are integrated into an efficient platform in a hardware/software codesign fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352/spl times/288) frames per second.

Platform architecture design for MPEG-4 video coding

This paper presents a cost-effective platform architecture design for MPEG-4 video coding. A fast motion estimator architecture supporting predictive diamond search and spiral full search with halfway termination is implemented to make good compromise between compression performance and design cost. An efficient block-level scheduling for texture coding engine is employed to reduce the hardware cost. Both these key modules are integrated into an efficient platform in hardware/software co-design fashion. With high degree of optimization in both algorithm and architecture levels, a cost-efficient video encoder is implemented. It consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352/spl times/288) frames per second.

A fast and high subjective quality sprite generation algorithm with frame skipping and multiple sprites techniques

Sprite coding, which is a new coding tool in MPEG-4, can achieve high coding efficiency with high subjective quality at low bit rate. Many sprite generation algorithms have been proposed; however, the computational intensity is very high and the quality is not good enough because of the limitation of simple motion models. A novel sprite generation algorithm is proposed with several new techniques. A frame skipping technique can generate the sprite using only several important frames to accelerate the process and achieve similar subjective quality. In addition, boundary matching and multiple sprites techniques can overcome the limitation of simple motion models to achieve high subjective quality with little computation overhead. Experiments show the proposed algorithm is 46 times faster than the algorithms in MPEG-4 VM and have high subjective quality. These techniques can be also applied with other sprite generation algorithms.

Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 Advanced Simple Profile

A cost-effective hardware architecture of integer, half, and quarter-pel motion estimation for MPEG-4 Advanced Simple Profile is proposed in this paper. Three-step hierarchy scheme is employed to cope with different pixel accuracy. For integer-pel estimation, the proposed computation-controllable algorithm makes it easy to be integrated into the coding system according to the power, quality, and timing conditions. For half and quarter-pel motion estimation, hardware-oriented algorithm and related architecture are proposed for cost reduction and provide 1.63 to 4.81 dB improvement in PSNR quality. The implementation takes 15K gates at 54MHz for sequences of CIF format at 30 fps.

Texture coder design of MPEG4 video by using interleaving schedule

For MPEG-4 texture coding, an efficient Interleaving DCT and IDCT Schedule (IDIS) is proposed. With this scheme, the DCT-Q-IQ-IDCT coding loop can be implemented with no buffers and least latency, which in turn makes the number of buffers for MC a minimum of two. Also by the characteristics of IDIS, a substructure sharing technique is applied for DC/AC prediction with Q and IQ to reduce hardware cost further. All the functions are integrated to comprise the block engine for texture coding operations in the MPEG-4 video standard. For a encoding sequence of 720/spl times/480 at 30 fps, real-time requirement can be achieved at 54 MHz. The proposed scheduling can be further applied to other video coding standards for a cost-effective SOC implementation.