Sheng-Lyang Jang
National Taiwan University of Science and Technology
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Featured researches published by Sheng-Lyang Jang.
IEEE Microwave and Wireless Components Letters | 2006
Yun-Hsueh Chuang; S.-H. Lee; R.-H. Yen; Sheng-Lyang Jang; Jian-Feng Lee; Miin-Horng Juang
A low voltage and wide locking range injection-locked frequency divider using a standard 0.18-/spl mu/m complementary metal oxide semiconductor (CMOS) process is presented. The wide locking range and the low-voltage operation are performed by adding an injection nMOS between the differential outputs of the divider that contains on-chip transformers which result in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. The measurement results show that at the supply voltage of 0.75-V, the divider free-running frequency is 2.02 GHz, and at the incident power of 0 dBm the locking range is about 1.49 GHz (36.88%), from the incident frequency 3.27 to 4.64GHz.
IEEE Microwave and Wireless Components Letters | 2009
Sheng-Lyang Jang; Yuan-Kai Wu; Cheng-Chen Liu; Jhin-Fang Huang
A new fully integrated, dual-band CMOS voltage controlled oscillator (VCO) is presented. The VCO is composed of n-core cross-coupled Colpitts VCOs and was implemented in 0.18 mum CMOS technology with 0.8 V supply voltage. The circuit allows the VCO to operate at two resonant frequencies with a common LC tank. The VCO has two control inputs, one for continuous control of the output frequency and one for band switching. This VCO is configured with 5 GHz and 12 GHz frequency bands with differential outputs. The dual-band VCO operates in 4.78-5.19 GHz and 12.19-12.61 GHz. The phase noises of the VCO operating at 5.11 and 12.2 GHz are -117.16 dBc/Hz and -112.15 dBc/Hz at 1 MHz offset, respectively, while the VCO draws 3.2/2.72 mA and 2.56/2.18 mW consumption at low/high frequency band from a 0.8 V supply.
IEEE Microwave and Wireless Components Letters | 2007
Shao-Hua Lee; Yun-Hsueh Chuang; Sheng-Lyang Jang; Chien-Cheng Chen
This letter presents a novel Hartley low phase noise differential CMOS voltage-controlled oscillator (VCO). The low noise CMOS VCO has been implemented with the TSMC 0.18-mum 1P6M CMOS technology and adopts full PMOS to achieve a better phase noise performance. The VCO operates from 4.02 to 4.5GHz with 11.3% tuning range. The measured phase noise at 1-MHz offset is about -119dBc/Hz at 4.02GHz and 122dBc/Hz at 4.5GHz. The power consumption of the VCO core is 6.75mW
IEEE Microwave and Wireless Components Letters | 2008
Sheng-Lyang Jang; Chien-Feng Lee; Wei-Hsung Yen
This letter proposes a new divide-by-3 CMOS injection locked frequency divider (ILFDMOS. ) fabricated in a 0.18-mum CMOS process and describes the operation principle of the ILFD. The ILFD circuit is realized with a double cross-coupled CMOS LC-tank oscillator with an injection MOS. The self-oscillating voltage controlled oscillator is injection-locked by third-harmonic input to obtain the division order of three. Measurement results show that at the supply voltage of 1.8 V, the free-running frequency is from 1.62 to 1.89 GHz. At the incident power of 5 dBm, the locking range is from the incident frequency 4.85 to 5.7 GHz.
IEEE Microwave and Wireless Components Letters | 2007
Yun-Hsueh Chuang; Sheng-Lyang Jang; S.-H. Lee; R.-H. Yen; J.-J. Jhao
This letter proposes 5-GHz low power differential Armstrong voltage controlled oscillators (VCOs) based on balanced topology. One designed VCO uses two single-ended Armstrong VCOs coupled to each other in parallel by balanced structure. The other current-reused VCO uses two single-ended Armstrong VCOs stacked in series. The former VCO oscillates from 4.96 to 5.34GHz and the power consumption is 3.9mW at 0.6-V supply voltage. The latter operates from 4.98 to 5.45GHz and dissipates 2.59mW at 1.8-V supply voltage. The measured phase noises are about -116.71dBc/Hz and -110.02dBc/Hz at 1-MHz offset frequency from 5.1-GHz band, respectively. The former and the latter VCO have an advantage of low power consumption and provide a good figure of merit of about -185dBc/Hz and -180dBc/Hz, respectively
IEEE Microwave and Wireless Components Letters | 2007
Shao-Hua Lee; Sheng-Lyang Jang; Yun-Hsueh Chung
This letter presents a low voltage quadrature divide-by-4 (divide4) injection-locked frequency divider (QILFD). The QILFD consists of a 1.8-GHz quadrature voltage controlled oscillator (QVCO) and two NMOS switches, which are inserted into the quadrature outputs of the QVCO for signal injection. The low-voltage CMOS divide4 QILFD has been implemented with the TSMC 0.18-mum 1P6 M CMOS technology and the core power consumption is 3.12mW at the supply voltage of 1.2V. The free-running frequency of the QILFD is tunable from 1.73 to 1.99GHz, the measured phase noise of QILFD is -118dBc/Hz at 1-MHz offset from the free running frequency of 1.82GHz. At the input power of 0dBm, the total locking range is from 6.86 to 8.02GHz as the tuning voltage is varied from 0 to 1.2V. The phase noise of the locked output spectrum is lower than that of free running ring oscillator by 11dBc/Hz. The phase deviation of quadrature output is about 0.8deg
IEEE Microwave and Wireless Components Letters | 2009
Sheng-Lyang Jang; Shin‐Hsin Huang; Cheng-Chen Liu; Miin-Horng Juang
This paper presents a new low phase noise quadrature voltage-controlled oscillator (QVCO), which consists of two differential complementary Colpitts voltage-controlled oscillators (VCOs) with a tail inductor. The output of the tail inductor in one differential VCO is injected to the bodies of the nMOSFETs in the other differential VCO and vice versa. The proposed CMOS QVCO has been implemented with the TSMC 0.18 mum CMOS technology and the die area is 0.725 times 0.839 mm2. At the supply voltage of 1.1 V, the total power consumption is 9.9 mW. The free-running frequency of the QVCO is tunable from 5.26 GHz to 5.477 GHz as the tuning voltage is varied from 0.0 V to 1.1 V. The measured phase noise at 1 MHz frequency offset is -124.36 dBc/Hz at the oscillation frequency of 5.44 GHz and the figure of merit (FOM) of the proposed QVCO is -189.1 dBc/Hz.
IEEE Microwave and Wireless Components Letters | 2006
Yun-Hsueh Chuang; S.-H. Lee; R.-H. Yen; Sheng-Lyang Jang; Miin-Horng Juang
A novel low-voltage quadrature voltage-controlled oscillator (QVCO) with voltage feedback to the input gate of a switching amplifier is proposed and implemented using the standard TSMC 0.18-mum CMOS 1P6M process. The proposed circuit topology is made up of two low-voltage LC-tank VCOs, where the coupled QVCO is obtained using the transformer coupling technique. At the 0.7-V supply voltage, the output phase noise of the VCO is -124.9 dBc/Hz at 1-MHz offset frequency from the carrier frequency of 2.4GHz, and the figure of merit is -185.35dBc/Hz. Total power consumption is 5.18 mW. Tuning range is about 135 MHz while the control voltage was tuned from 0 to 0.7V
IEEE Microwave and Wireless Components Letters | 2007
Sheng-Lyang Jang; Chein-Feng Lee
A 1.1-GHz voltage control oscillator (VCO) using a standard 0.18-mum CMOS 1P6M process is fabricated. The VCO was designed with dynamic threshold voltage metal-oxide-semiconductor field-effect transistors and extremely-low-voltage and low power operation is achieved using on-chip transformers in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. This VCO prototype is designed for a 0.34-V supply voltage while the output phase noise is -121.2dBc/Hz at 1-MHz offset frequency at the carrier frequency of 1.14GHz, the figure of merit is -192.0dB. The total power consumption is 103.7muW with the 0.34-V supply voltage. Tuning range is from 1.06 to 1.14GHz about 80MHz while the control voltage was tuned from 0 to 1.8V. The die area is 0.625times0.79mm2
IEEE Microwave and Wireless Components Letters | 2010
Sheng-Lyang Jang; Chia-Wei Chang
This letter proposes a wide-locking range divide-by-3 injection-locked frequency divider fabricated in the 90 nm 1P9M CMOS technology. The divider consists of an nMOS cross-coupled p-core Armstrong LC oscillator and a center-tapped inductor in series with the pMOSFETs. The pMOSFETs are used as a linear and second harmonic mixer. At the supply voltage of 1 V, the free-running frequency is from 7.84 to 8.42 GHz, the current and power consumption of the divider without buffers are 4 mA and 4 mW respectively. At the incident power of 0 dBm, the locking range is 4.28 GHz (19.8%), from the incident frequency 19.52 to 23.8 GHz.