Wen Ji

Data conflict resolution for layered LDPC decoding algorithm by selective recalculation

Layered LDPC decoding algorithm is known to achieve high Bit Error Rate (BER) performance and high throughput for LDPC decoders. However, for ISDB-S2 (Integrated Services Digital Broadcasting via Satellite - Second Generation) LDPC decoder, applying layered algorithm directly will result in data conflict problem. In this paper, a novel selective recalculation method is proposed to solve the data conflict problem. It determines the inaccurately calculated values based on a recalculation decision rule, and correct them accordingly. By applying this selective recalculation method, the layered algorithm can achieve conflict free BER performance. Simulation results demonstrate that the proposed method can achieve 0.1dB gain for the code with most conflicts in ISDB-S2, under the same BER performance compared to the previous strategy to solve data conflict problem.

Self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder

In this paper, a novel self-adjustable offset min-sum LDPC decoding algorithm is proposed for ISDB-S2 (Integrated Services Digital Broadcasting via Satellite - Second Generation) application. We present for the first time a uniform approximation of the check node operation through mathematical induction on Jacobian logarithm. The approximation theoretically shows that the offset value is mainly dependent on the difference between the two most unreliable inputs from the bit nodes and the algorithm proposed can adjust the offset value according to the inputs during the iterative decoding procedure. Simulation results for all 11 code rates of ISDB-S2 demonstrate that the proposed method can achieve an average of 0.15dB gain under the same Bit Error Rate (BER) performance, compared to the Min-sum based algorithms, and consumes only 1.21% computation complexity compared to BP-based algorithms in the best case.

A high performance LDPC decoder for IEEE802.11n standard

In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

A High Throughput LDPC Decoder Design Based on Novel Delta-value Message-passing Schedule

In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard targeting high throughput applications. The proposed decoder has several merits: (i) The decoder is designed based on a novel delta-value based message passing algorithm which facilitates the decoding throughput by redundant computation removal. (ii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648, 324) irregular LDPC code, our decoder can achieve 8 times increasement in throughput, reaching 418Mbps at the frequency of 200MHz.

High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message- passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200 MHz.

A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm

A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.